diff --git a/sys/arch/arm/cortex/armperiph.c b/sys/arch/arm/cortex/armperiph.c index a150a55..cdfe6bc 100644 --- a/sys/arch/arm/cortex/armperiph.c +++ b/sys/arch/arm/cortex/armperiph.c @@ -69,7 +69,11 @@ static const struct armperiph_info a5_devices[] = { #ifdef CPU_CORTEXA7 static const struct armperiph_info a7_devices[] = { +#ifdef ARM_KVM_GUEST + { "armvgic", 0x1000, 0x2000 }, +#else { "armgic", 0x1000, 0x2000 }, +#endif { "armgtmr", 0, 0 }, { "", 0, 0 }, }; @@ -88,7 +92,11 @@ static const struct armperiph_info a9_devices[] = { #ifdef CPU_CORTEXA15 static const struct armperiph_info a15_devices[] = { +#ifdef ARM_KVM_GUEST + { "armvgic", 0x1000, 0x2000 }, +#else { "armgic", 0x1000, 0x2000 }, +#endif { "armgtmr", 0, 0 }, { "", 0, 0 }, }; @@ -154,8 +162,10 @@ armperiph_match(device_t parent, cfdata_t cf, void *aux) if (!CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid)) return 0; +#ifndef ARM_KVM_GUEST if (armreg_cbar_read() == 0) return 0; +#endif if (armperiph_find_config() == NULL) return 0; diff --git a/sys/arch/arm/cortex/files.cortex_kvm b/sys/arch/arm/cortex/files.cortex_kvm new file mode 100644 index 0000000..724af9a --- /dev/null +++ b/sys/arch/arm/cortex/files.cortex_kvm @@ -0,0 +1,21 @@ +# $NetBSD$ + +defflag opt_cpu_in_cksum.h NEON_IN_CKSUM + +file arch/arm/cortex/cpu_in_cksum_neon.c (inet | inet6) & neon_in_cksum +file arch/arm/cortex/cpu_in_cksum_asm_neon.S (inet | inet6) & neon_in_cksum + +device armperiph {} +attach armperiph at mainbus +file arch/arm/cortex/armperiph.c armperiph + +# ARM/KVM vGIC +device armvgic: pic, pic_splfuncs +attach armvgic at armperiph +file arch/arm/cortex/vgic.c armvgic + +# ARMv7 Generic Timer +device armgtmr +attach armgtmr at armperiph +file arch/arm/cortex/gtmr.c armgtmr + diff --git a/sys/arch/arm/cortex/vgic.c b/sys/arch/arm/cortex/vgic.c new file mode 100644 index 0000000..75e4e7d --- /dev/null +++ b/sys/arch/arm/cortex/vgic.c @@ -0,0 +1,372 @@ +/* $NetBSD$ */ + +/*- + * Copyright (c) 2015 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Sergio L. Pascual. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "opt_ddb.h" +#include "opt_multiprocessor.h" + +#define _INTR_PRIVATE + +#include +__KERNEL_RCSID(0, "$NetBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#define ARMGIC_SGI_IPIBASE (16 - NIPI) + +static int armvgic_match(device_t, cfdata_t, void *); +static void armvgic_attach(device_t, device_t, void *); + +static void armvgic_unblock_irqs(struct pic_softc *, size_t, uint32_t); +static void armvgic_block_irqs(struct pic_softc *, size_t, uint32_t); +static int armvgic_find_pending_irqs(struct pic_softc *, void *frame); +static void armvgic_establish_irq(struct pic_softc *, struct intrsource *); + +static const struct pic_ops armvgic_picops = { + .pic_unblock_irqs = armvgic_unblock_irqs, + .pic_block_irqs = armvgic_block_irqs, + .pic_establish_irq = armvgic_establish_irq, +}; +#define PICTOSOFTC(pic) ((struct armvgic_softc *)(pic)) + +static struct armvgic_softc { + struct pic_softc sc_pic; + device_t sc_dev; + bus_space_tag_t sc_memt; + bus_space_handle_t sc_gicch; + bus_space_handle_t sc_gicdh; + size_t sc_gic_lines; + uint32_t sc_gic_type; + uint32_t sc_gic_valid_lines[1024 / 32]; +} armvgic_softc = { + .sc_pic = { + .pic_ops = &armvgic_picops, + .pic_name = "armvgic", + }, +}; + +static struct intrsource armvgic_dummy_source; + +__CTASSERT(NIPL == 8); + +/* + * GIC register are always in little-endian. It is assumed the bus_space + * will do any endian conversion required. + */ +static inline uint32_t +gicc_read(struct armvgic_softc * sc, bus_size_t o) +{ + return bus_space_read_4(sc->sc_memt, sc->sc_gicch, o); +} + +static inline void +gicc_write(struct armvgic_softc * sc, bus_size_t o, uint32_t v) +{ + bus_space_write_4(sc->sc_memt, sc->sc_gicch, o, v); +} + +static inline uint32_t +gicd_read(struct armvgic_softc * sc, bus_size_t o) +{ + return bus_space_read_4(sc->sc_memt, sc->sc_gicdh, o); +} + +static inline void +gicd_write(struct armvgic_softc * sc, bus_size_t o, uint32_t v) +{ + bus_space_write_4(sc->sc_memt, sc->sc_gicdh, o, v); +} + +static void +armvgic_unblock_irqs(struct pic_softc * pic, size_t irq_base, uint32_t irq_mask) +{ + struct armvgic_softc *const sc = PICTOSOFTC(pic); + for (;;) { + int irq = ffs(irq_mask); + if (irq-- == 0) + return; + + gicc_write(sc, GICC_EOIR, irq + irq_base); + irq_mask &= ~__BIT(irq); + } +} + +static void +armvgic_block_irqs(struct pic_softc * pic, size_t irq_base, uint32_t irq_mask) +{ + /* + * Here we should disable the interrupt in the distributor, but + * writing to it is expensive, as it traps to the host. Instead, + * we don't signal EOI until armvgic_unblock_irqs, leaving the + * interrupt in active state until we finish processing it. + */ +} + +#ifdef __HAVE_PIC_FAST_SOFTINTS +void +softint_init_md(lwp_t * l, u_int level, uintptr_t * machdep_p) +{ + lwp_t **lp = &l->l_cpu->ci_softlwps[level]; + KASSERT(*lp == NULL || *lp == l); + *lp = l; + /* + * Really easy. Just tell it to trigger the local CPU. + */ + *machdep_p = GICD_SGIR_TargetListFilter_Me + | __SHIFTIN(level, GICD_SGIR_SGIINTID); +} + +void +softint_trigger(uintptr_t machdep) +{ + + gicd_write(&armvgic_softc, GICD_SGIR, machdep); +} +#endif + +static int +armvgic_find_pending_irqs(struct pic_softc * pic, void *frame) +{ + struct armvgic_softc *sc = PICTOSOFTC(pic); + uint32_t pending_group0, pending_group1; + int ipl = 0; + + pending_group0 = pending_group1 = 0; + + for (;;) { + uint32_t iar = gicc_read(sc, GICC_IAR); + uint32_t irq = __SHIFTOUT(iar, GICC_IAR_IRQ); + + if (irq == GICC_IAR_IRQ_SPURIOUS) + break; + + struct intrsource *const is = sc->sc_pic.pic_sources[irq]; + KASSERT(is != &armvgic_dummy_source); + + if (is->is_arg == NULL) { + is->is_arg = frame; + } + if (irq < 32) { + pending_group0 |= 1 << irq; + } else { + pending_group1 |= 1 << (irq - 32); + } + } + + ipl |= pic_mark_pending_sources(pic, 0, pending_group0); + ipl |= pic_mark_pending_sources(pic, 32, pending_group1); + + return ipl; +} + +void +armvgic_irq_handler(void *frame) +{ + struct cpu_info *const ci = curcpu(); + const int oldipl = ci->ci_cpl; + const uint32_t oldipl_mask = __BIT(oldipl); + int ipl_mask = 0; + + ipl_mask = armvgic_find_pending_irqs(&armvgic_softc.sc_pic, frame); + + /* + * Record the pending_ipls and deliver them if we can. + */ + if ((ipl_mask & ~oldipl_mask) > oldipl_mask) + pic_do_pending_ints(I32_bit, oldipl, frame); +} + +void +armvgic_establish_irq(struct pic_softc * pic, struct intrsource * is) +{ + struct armvgic_softc *const sc = PICTOSOFTC(pic); + const size_t group = is->is_irq / 32; + const u_int irq = is->is_irq & 31; + const u_int byte_shift = 8 * (irq & 3); + const u_int twopair_shift = 2 * (irq & 15); + + KASSERTMSG(sc->sc_gic_valid_lines[group] & __BIT(irq), + "irq %u: not valid (group[%zu]=0x%08x [0x%08x])", + is->is_irq, group, sc->sc_gic_valid_lines[group], + (uint32_t) __BIT(irq)); + + KASSERTMSG(is->is_type == IST_LEVEL || is->is_type == IST_EDGE, + "irq %u: type %u unsupported", is->is_irq, is->is_type); + + const bus_size_t targets_reg = GICD_ITARGETSRn(is->is_irq / 4); + const bus_size_t cfg_reg = GICD_ICFGRn(is->is_irq / 16); + uint32_t targets = gicd_read(sc, targets_reg); + uint32_t cfg = gicd_read(sc, cfg_reg); + + if (group > 0) { + /* There are 4 irqs per TARGETS register. For now bind to the + * primary cpu. */ + targets &= ~(0xff << byte_shift); + targets |= 1 << byte_shift; + gicd_write(sc, targets_reg, targets); + + /* There are 16 irqs per CFG register. 10=EDGE 00=LEVEL */ + uint32_t new_cfg = cfg; + uint32_t old_cfg = (cfg >> twopair_shift) & 3; + if (is->is_type == IST_LEVEL && (old_cfg & 2) != 0) { + new_cfg &= ~(3 << twopair_shift); + } else if (is->is_type == IST_EDGE && (old_cfg & 2) == 0) { + new_cfg |= 2 << twopair_shift; + } + if (new_cfg != cfg) { + gicd_write(sc, cfg_reg, cfg); + } + } +} + +int +armvgic_match(device_t parent, cfdata_t cf, void *aux) +{ + struct mpcore_attach_args *const mpcaa = aux; + + if (strcmp(cf->cf_name, mpcaa->mpcaa_name) != 0) + return 0; + if (!CPU_ID_CORTEX_P(cputype) || CPU_ID_CORTEX_A8_P(cputype)) + return 0; + + return 1; +} + +void +armvgic_attach(device_t parent, device_t self, void *aux) +{ + struct armvgic_softc *const sc = &armvgic_softc; + struct mpcore_attach_args *const mpcaa = aux; + + sc->sc_dev = self; + self->dv_private = sc; + + sc->sc_memt = mpcaa->mpcaa_memt; /* provided for us */ + bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, mpcaa->mpcaa_off1, + 4096, &sc->sc_gicdh); + bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, mpcaa->mpcaa_off2, + 4096, &sc->sc_gicch); + + sc->sc_gic_type = gicd_read(sc, GICD_TYPER); + sc->sc_pic.pic_maxsources = GICD_TYPER_LINES(sc->sc_gic_type); + + gicc_write(sc, GICC_CTRL, 0); /* disable all interrupts */ + gicd_write(sc, GICD_CTRL, 0); /* disable all interrupts */ + + gicc_write(sc, GICC_PMR, 0xff); + uint32_t pmr = gicc_read(sc, GICC_PMR); + u_int priorities = 1 << popcount32(pmr); + + /* + * Let's find out how many real sources we have. + */ + for (size_t i = 0, group = 0; + i < sc->sc_pic.pic_maxsources; + i += 32, group++) { + /* + * To figure what sources are real, one enables all interrupts + * and then reads back the enable mask so which ones really + * got enabled. + */ + gicd_write(sc, GICD_ISENABLERn(group), 0xffffffff); + uint32_t valid = gicd_read(sc, GICD_ISENABLERn(group)); + + /* + * Count how many are valid. + */ + sc->sc_gic_lines += popcount32(valid); + sc->sc_gic_valid_lines[group] = valid; + } + + aprint_normal(": Generic Interrupt Controller, " + "%zu sources (%zu valid)\n", + sc->sc_pic.pic_maxsources, sc->sc_gic_lines); + + pic_add(&sc->sc_pic, 0); + + /* + * Force the GICD to IPL_HIGH and then enable interrupts. + */ + struct cpu_info *const ci = curcpu(); + KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl); + gicd_write(sc, GICD_CTRL, GICD_CTRL_Enable); + //enable Distributer + gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); + //enable CPU interrupts + cpsie(I32_bit); + //allow interrupt exceptions + + /* + * For each line that isn't valid, we set the intrsource for it to + * point at a dummy source so that pic_intr_establish will fail for it. + */ + for (size_t i = 0, group = 0; + i < sc->sc_pic.pic_maxsources; + i += 32, group++) { + uint32_t invalid = ~sc->sc_gic_valid_lines[group]; + for (size_t j = 0; invalid && j < 32; j++, invalid >>= 1) { + if (invalid & 1) { + sc->sc_pic.pic_sources[i + j] = + &armvgic_dummy_source; + } + } + } +#ifdef __HAVE_PIC_FAST_SOFTINTS + intr_establish(SOFTINT_BIO, IPL_SOFTBIO, IST_EDGE, + pic_handle_softint, (void *) SOFTINT_BIO); + intr_establish(SOFTINT_CLOCK, IPL_SOFTCLOCK, IST_EDGE, + pic_handle_softint, (void *) SOFTINT_CLOCK); + intr_establish(SOFTINT_NET, IPL_SOFTNET, IST_EDGE, + pic_handle_softint, (void *) SOFTINT_NET); + intr_establish(SOFTINT_SERIAL, IPL_SOFTSERIAL, IST_EDGE, + pic_handle_softint, (void *) SOFTINT_SERIAL); +#endif + + const u_int ppis = popcount32(sc->sc_gic_valid_lines[0] >> 16); + const u_int sgis = popcount32(sc->sc_gic_valid_lines[0] & 0xffff); + aprint_normal_dev(sc->sc_dev, "%u Priorities, %zu SPIs, %u PPIs, %u SGIs\n", + priorities, sc->sc_gic_lines - ppis - sgis, ppis, sgis); +} + +CFATTACH_DECL_NEW(armvgic, 0, + armvgic_match, armvgic_attach, NULL, NULL); diff --git a/sys/arch/arm/cortex/vgic_intr.h b/sys/arch/arm/cortex/vgic_intr.h new file mode 100644 index 0000000..1fa720b --- /dev/null +++ b/sys/arch/arm/cortex/vgic_intr.h @@ -0,0 +1,61 @@ +/* $NetBSD$ */ + +/*- + * Copyright (c) 2015 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Sergio L. Pascual. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM_CORTEX_VGIC_INTR_H_ +#define _ARM_CORTEX_VGIC_INTR_H_ + +#define ARM_IRQ_HANDLER _C_LABEL(armvgic_irq_handler) + +#ifndef _LOCORE + +#if defined(__HAVE_FAST_SOFTINTS) && 0 +#define __HAVE_PIC_FAST_SOFTINTS +#endif + +#ifndef PIC_MAXSOURCES +#error PIC_MAXSOURCES needs to be defined +#endif +#ifndef PIC_MAXMAXSOURCES +#error PIC_MAXMAXSOURCES needs to be defined +#endif + +#define IRQ_SGI(n) ( 0 + ((n) & 15)) +#define IRQ_PPI(n) (16 + ((n) & 15)) +#define IRQ_SPI(n) (32 + (n)) +#define GIC_MAXSOURCES(n) IRQ_SPI(n) + +void armvgic_irq_handler(void *); + +#include + +#endif + +#endif /* _ARM_CORTEX_VGIC_INTR_H_ */ diff --git a/sys/arch/evbarm/conf/VEXPRESS_A15_KVM b/sys/arch/evbarm/conf/VEXPRESS_A15_KVM new file mode 100644 index 0000000..88165a3 --- /dev/null +++ b/sys/arch/evbarm/conf/VEXPRESS_A15_KVM @@ -0,0 +1,218 @@ +# +# $NetBSD$ +# +# VEXPRESS_A15 -- Versatile Express A15 kernel +# + +include "arch/evbarm/conf/std.vexpress_kvm" + +# estimated number of users + +maxusers 32 + +# Standard system options + +options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT +#options NTP # NTP phase/frequency locked loop + +# CPU options +options CPU_CORTEX +options CPU_CORTEXA7 +options CPU_CORTEXA15 +#options MULTIPROCESSOR +options ARM_KVM_GUEST + +options PMAPCOUNTERS +options BUSDMA_COUNTERS +#options EXYNOS_CONSOLE_EARLY +#options UVMHIST +#options USBHIST +#options USBHIST_SIZE=100000 +#options UVMHIST_PRINT,KERNHIST_DELAY=0 +options __HAVE_MM_MD_DIRECT_MAPPED_PHYS +options PMAP_NEED_ALLOC_POOLPAGE + +# Specify the memory size in megabytes (optional). +#options MEMSIZE=512 + +# File systems +file-system FFS # UFS +#file-system LFS # log-structured file system +file-system MFS # memory file system +file-system NFS # Network file system +#file-system ADOSFS # AmigaDOS-compatible file system +#file-system EXT2FS # second extended file system (linux) +#file-system CD9660 # ISO 9660 + Rock Ridge file system +file-system MSDOSFS # MS-DOS file system +#file-system FDESC # /dev/fd +file-system KERNFS # /kern +#file-system NULLFS # loopback file system +file-system PROCFS # /proc +#file-system PUFFS # Userspace file systems (e.g. ntfs-3g & sshfs) +#file-system UMAPFS # NULLFS + uid and gid remapping +#file-system UNION # union file system +file-system TMPFS # memory file system +file-system PTYFS # /dev/pts/N support + +# File system options +#options QUOTA # legacy UFS quotas +#options QUOTA2 # new, in-filesystem UFS quotas +#options FFS_EI # FFS Endian Independent support +#options NFSSERVER +options WAPBL # File system journaling support +#options FFS_NO_SNAPSHOT # No FFS snapshot support + +# Networking options + +#options GATEWAY # packet forwarding +options INET # IP + ICMP + TCP + UDP +options INET6 # IPV6 +#options IPSEC # IP security +#options IPSEC_DEBUG # debug for IP security +#options MROUTING # IP multicast routing +#options PIM # Protocol Independent Multicast +#options NETATALK # AppleTalk networking +#options PPP_BSDCOMP # BSD-Compress compression support for PPP +#options PPP_DEFLATE # Deflate compression support for PPP +#options PPP_FILTER # Active filter support for PPP (requires bpf) +#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG + +options NFS_BOOT_BOOTP +options NFS_BOOT_DHCP +#options NFS_BOOT_BOOTSTATIC +#options NFS_BOOTSTATIC_MYIP="\"192.168.1.4\"" +#options NFS_BOOTSTATIC_GWIP="\"192.168.1.1\"" +#options NFS_BOOTSTATIC_MASK="\"255.255.255.0\"" +#options NFS_BOOTSTATIC_SERVADDR="\"192.168.1.1\"" +#options NFS_BOOTSTATIC_SERVER="\"192.168.1.1:/nfs/sdp2430\"" + +options NFS_BOOT_RWSIZE=1024 + +# Compatibility options + +options COMPAT_NETBSD32 # allow running arm (e.g. non-earm) binaries +#options COMPAT_43 # 4.3BSD compatibility. +#options COMPAT_09 # NetBSD 0.9, +#options COMPAT_10 # NetBSD 1.0, +#options COMPAT_11 # NetBSD 1.1, +#options COMPAT_12 # NetBSD 1.2, +#options COMPAT_13 # NetBSD 1.3, +#options COMPAT_14 # NetBSD 1.4, +#options COMPAT_15 # NetBSD 1.5, +#options COMPAT_16 # NetBSD 1.6, +#options COMPAT_20 # NetBSD 2.0, +options COMPAT_30 # NetBSD 3.0, +options COMPAT_40 # NetBSD 4.0, +options COMPAT_50 # NetBSD 5.0, +options COMPAT_60 # NetBSD 6.0, and +options COMPAT_70 # NetBSD 7.0 binary compatibility. +#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended. +#options COMPAT_BSDPTY # /dev/[pt]ty?? ptys. + +# Shared memory options + +options SYSVMSG # System V-like message queues +options SYSVSEM # System V-like semaphores +options SYSVSHM # System V-like memory sharing + +# Device options + +#options MEMORY_DISK_HOOKS # boottime setup of ramdisk +#options MEMORY_DISK_ROOT_SIZE=8192 # Size in blocks +#options MEMORY_DISK_DYNAMIC +#options MINIROOTSIZE=1000 # Size in blocks +#options MEMORY_DISK_IS_ROOT # use memory disk as root + +# Wedge support +options DKWEDGE_AUTODISCOVER # Automatically add dk(4) instances +options DKWEDGE_METHOD_GPT # Supports GPT partitions as wedges + +# Miscellaneous kernel options +options KTRACE # system call tracing, a la ktrace(1) +#options KMEMSTATS # kernel memory statistics +#options SCSIVERBOSE # Verbose SCSI errors +options MIIVERBOSE # Verbose MII autoconfuration messages +#options DDB_KEYCODE=0x40 +#options USERCONF # userconf(4) support +#options PIPE_SOCKETPAIR # smaller, but slower pipe(2) + +# Development and Debugging options + +#options PERFCTRS # performance counters +options DIAGNOSTIC # internal consistency checks +options DEBUG +options LOCKDEBUG +#options PMAP_DEBUG # Enable pmap_debug_level code +#options IPKDB # remote kernel debugging +options VERBOSE_INIT_ARM # verbose bootstraping messages +options DDB # in-kernel debugger +options DDB_ONPANIC=1 +options DDB_HISTORY_SIZE=100 # Enable history editing in DDB +#options KGDB +makeoptions DEBUG="-g" # compile full symbol table +makeoptions COPY_SYMTAB=1 +options PLCONSOLE + +# Valid options for BOOT_ARGS: +# single Boot to single user only +# kdb Give control to kernel debugger +# ask Ask for file name to reboot from +# memorydisk= Set memorydisk size to KB +# quiet Show aprint_naive output +# verbose Show aprint_normal and aprint_verbose output +#options BOOT_ARGS="\"\"" +options BOOT_ARGS="\"verbose\"" + +config netbsd root on ? type ? + +# The main bus device +mainbus0 at root + +# The boot cpu and secondary CPUs +cpu0 at mainbus? +#cpu? at mainbus? # Multiprocessor + +# A9 core devices +armperiph0 at mainbus? +armvgic0 at armperiph? # KVM vGIC +armgtmr0 at armperiph? # Generic Timer + +# VEXPRESS AXI0 +axi0 at mainbus? + +# PL011 uart +plcom0 at axi? addr 0x1c090000 irq 37 + +# PL181 MMCI host controller +plmmc0 at axi? addr 0x1c050000 irq 41 +sdmmc* at plmmc0 +ld* at sdmmc? +#options SDMMC_DEBUG +#options SDMMCCISDEBUG + +# LAN 9118 +smsh0 at axi? addr 0x1a000000 irq 47 + +# MII/PHY support +ukphy* at mii? phy ? # smsh(4) internal PHY + +# Pseudo-Devices + +# disk/mass storage pseudo-devices +#pseudo-device md # memory disk device (ramdisk) +#pseudo-device vnd # disk-like interface to files +#pseudo-device fss # file system snapshot device +#pseudo-device putter # for puffs and pud +pseudo-device drvctl # driver control + +# network pseudo-devices +pseudo-device bpfilter # Berkeley packet filter +pseudo-device loop # network loopback +#pseudo-device kttcp # network loopback + +# miscellaneous pseudo-devices +pseudo-device pty # pseudo-terminals +#options RND_COM +#pseudo-device clockctl # user control of clock subsystem +pseudo-device ksyms # /dev/ksyms +#pseudo-device lockstat # lock profiling diff --git a/sys/arch/evbarm/conf/files.vexpress_kvm b/sys/arch/evbarm/conf/files.vexpress_kvm new file mode 100644 index 0000000..7334743 --- /dev/null +++ b/sys/arch/evbarm/conf/files.vexpress_kvm @@ -0,0 +1,34 @@ +# $NetBSD$ +# +# Versatile Express board configuration info +# + +file arch/evbarm/vexpress/vexpress_machdep.c + +include "arch/arm/pic/files.pic" +include "arch/arm/cortex/files.cortex_kvm" + +file arch/arm/arm32/arm32_boot.c +file arch/arm/arm32/arm32_kvminit.c +file arch/arm/arm32/arm32_reboot.c +file arch/arm/arm32/irq_dispatch.S + +file arch/evbarm/vexpress/vexpress_space.c + +# VEXPRESS AXI/AHB bus interface and SoC domains +device axi { [addr=-1], [size=0], [irq=-1], [irqbase=-1]} : bus_space_generic +attach axi at mainbus +file arch/evbarm/vexpress/vexpress_axi.c axi + +# UART Interface +attach plcom at axi with vexpressplcom +file arch/evbarm/vexpress/vexpress_plcom.c vexpressplcom + +# MMCI host controller +attach plmmc at axi with vexpressplmmc +file arch/evbarm/vexpress/vexpress_plmmc.c vexpressplmmc + +# SMSC LAN9118 +attach smsh at axi with smsh_axi +file arch/evbarm/vexpress/if_smsh_axi.c smsh_axi + diff --git a/sys/arch/evbarm/conf/std.vexpress_kvm b/sys/arch/evbarm/conf/std.vexpress_kvm new file mode 100644 index 0000000..27ce05e --- /dev/null +++ b/sys/arch/evbarm/conf/std.vexpress_kvm @@ -0,0 +1,32 @@ +# $NetBSD$ +# +# standard NetBSD/evbarm for VEXPRESS/KVM options + +machine evbarm arm +include "arch/evbarm/conf/std.evbarm" + +# Pull in VEXPRESS config definitions +include "arch/evbarm/conf/files.vexpress_kvm" + +makeoptions CPUFLAGS="-march=armv7-a -mfpu=neon" + +# To support easy transit to ../arch/arm/arm32 +options MODULAR +options MODULAR_DEFAULT_AUTOLOAD +options ARM_HAS_VBAR +options CORTEX_PMC +options __HAVE_CPU_COUNTER +options __HAVE_FAST_SOFTINTS # should be in types.h +#options __HAVE_MM_MD_DIRECT_MAPPED_PHYS +options TPIDRPRW_IS_CURCPU +options KERNEL_BASE_EXT=0x80000000 +options FPU_VFP + +makeoptions KERNEL_BASE_PHYS="0x80000000" +makeoptions KERNEL_BASE_VIRT="0x80000000" +makeoptions BOARDTYPE="vexpress" +makeoptions BOARDMKFRAG="${THISARM}/conf/mk.vexpress" + +options ARM_INTR_IMPL="" +options ARM_GENERIC_TODR +