diff --git a/sys/arch/riscv/riscv/bus_dma.c b/sys/arch/riscv/riscv/bus_dma.c
index a725bbe1a9c1..1ec003a2b302 100644
--- a/sys/arch/riscv/riscv/bus_dma.c
+++ b/sys/arch/riscv/riscv/bus_dma.c
@@ -1170,34 +1170,32 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
 	if ((map->_dm_flags & _BUS_DMAMAP_COHERENT)) {
 		switch (ops) {
 		case BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE:
+			asm volatile ("fence rw,ow" ::: "memory");
 			STAT_INCR(sync_coherent_prereadwrite);
 			break;
 
 		case BUS_DMASYNC_PREREAD:
+			asm volatile ("fence rw,ow" ::: "memory");
 			STAT_INCR(sync_coherent_preread);
 			break;
 
 		case BUS_DMASYNC_PREWRITE:
+			asm volatile ("fence w,ow" ::: "memory");
 			STAT_INCR(sync_coherent_prewrite);
 			break;
 
 		case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE:
+			asm volatile ("fence ir,r" ::: "memory");
 			STAT_INCR(sync_coherent_postreadwrite);
 			break;
 
 		case BUS_DMASYNC_POSTREAD:
+			asm volatile ("fence ir,r" ::: "memory");
 			STAT_INCR(sync_coherent_postread);
 			break;
 
 		/* BUS_DMASYNC_POSTWRITE was aleady handled as a fastpath */
 		}
-		/*
-		 * Drain the write buffer of DMA operators.
-		 * 1) when cpu->device (prewrite)
-		 * 2) when device->cpu (postread)
-		 */
-		if ((pre_ops & BUS_DMASYNC_PREWRITE) || (post_ops & BUS_DMASYNC_POSTREAD))
-			asm volatile ("fence iorw,iorw" ::: "memory");
 
 		/*
 		 * Only thing left to do for COHERENT mapping is copy from bounce