From d6a70690f1a0e2945d0f18d96eaea543cc9c7a32 Mon Sep 17 00:00:00 2001 From: Taylor R Campbell Date: Sun, 19 Feb 2023 16:17:04 +0000 Subject: [PATCH] mips: Issue a store-before-store barrier in cpu_switchto. Otherwise mutexes don't work. --- sys/arch/mips/mips/locore.S | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/sys/arch/mips/mips/locore.S b/sys/arch/mips/mips/locore.S index 87b8e6ed0f73..bbd9caf43fcf 100644 --- a/sys/arch/mips/mips/locore.S +++ b/sys/arch/mips/mips/locore.S @@ -288,6 +288,17 @@ NESTED(cpu_switchto, CALLFRAME_SIZ, ra) nop # patchable load delay slot PTR_S MIPS_CURLWP, CPU_INFO_CURLWP(t2) + /* + * kern_mutex.c requires a store-before-store barrier before + * any logic can resume in this thread. It may be necessary + * (though this is unclear to me) for this to happen before + * re-enabling interrupts too. SYNC_REL is stronger than + * needed (load/store-before-store) but that's not harmful + * and most MIPS doesn't have anything weaker than full sync + * anyway. + */ + SYNC_REL + /* Check for restartable atomic sequences (RAS) */ PTR_L a0, L_PROC(MIPS_CURLWP) # argument to ras_lookup PTR_L s5, L_PCB(MIPS_CURLWP) # XXXuvm_lwp_getuarea