From 79cf741c31b545f3fefcbfe309a027cabf7a3a17 Mon Sep 17 00:00:00 2001 From: Taylor R Campbell Date: Sat, 24 Apr 2021 12:05:13 +0000 Subject: [PATCH] arm/sunxi: Wire up sun8icrypto(4) on Allwinner H5. Tested on NanoPi Neo PLUS2. --- sys/arch/arm/dts/sun50i-h5.dtsi | 13 +++++++++++++ sys/arch/arm/sunxi/sun8i_crypto.c | 1 + sys/arch/arm/sunxi/sun8i_h3_ccu.c | 12 ++++++++++++ 3 files changed, 26 insertions(+) diff --git a/sys/arch/arm/dts/sun50i-h5.dtsi b/sys/arch/arm/dts/sun50i-h5.dtsi index 606a960fad63..bcd28f1cb74b 100644 --- a/sys/arch/arm/dts/sun50i-h5.dtsi +++ b/sys/arch/arm/dts/sun50i-h5.dtsi @@ -28,6 +28,19 @@ #include "sun8i-h3.dtsi" +/ { + soc { + crypto: crypto@1c15000 { + compatible = "allwinner,sun50i-h5-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CE>; + }; + }; +}; + &rtp { compatible = "allwinner,sun50i-h5-ts"; }; diff --git a/sys/arch/arm/sunxi/sun8i_crypto.c b/sys/arch/arm/sunxi/sun8i_crypto.c index 7428dc649fad..023b0fdc7f72 100644 --- a/sys/arch/arm/sunxi/sun8i_crypto.c +++ b/sys/arch/arm/sunxi/sun8i_crypto.c @@ -320,6 +320,7 @@ CFATTACH_DECL_NEW(sun8i_crypto, sizeof(struct sun8i_crypto_softc), static const struct device_compatible_entry compat_data[] = { { .compat = "allwinner,sun50i-a64-crypto" }, + { .compat = "allwinner,sun50i-h5-crypto" }, DEVICE_COMPAT_EOL }; diff --git a/sys/arch/arm/sunxi/sun8i_h3_ccu.c b/sys/arch/arm/sunxi/sun8i_h3_ccu.c index 292c90e0f48e..42bb1ea668f5 100644 --- a/sys/arch/arm/sunxi/sun8i_h3_ccu.c +++ b/sys/arch/arm/sunxi/sun8i_h3_ccu.c @@ -60,6 +60,7 @@ __KERNEL_RCSID(1, "$NetBSD: sun8i_h3_ccu.c,v 1.17 2021/01/27 03:10:20 thorpej Ex #define SDMMC0_CLK_REG 0x088 #define SDMMC1_CLK_REG 0x08c #define SDMMC2_CLK_REG 0x090 +#define CE_CLK_REG 0x09c #define SPI0_CLK_REG 0x0a0 #define SPI1_CLK_REG 0x0a4 #define USBPHY_CFG_REG 0x0cc @@ -154,6 +155,7 @@ static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; static const char *apb1_parents[] = { "ahb1" }; static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; +static const char *ce_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" }; static const char *mod_parents[] = { "hosc", "pll_periph0", "pll_periph1" }; static const char *ths_parents[] = { "hosc" }; static const char *de_parents[] = { "pll_periph0_2x", "pll_de" }; @@ -329,6 +331,14 @@ static struct sunxi_ccu_clk sun8i_h3_ccu_clks[] = { 0, /* enable */ SUNXI_CCU_NM_POWER_OF_TWO), + SUNXI_CCU_NM(H3_CLK_CE, "ce", ce_parents, + CE_CLK_REG, /* reg */ + __BITS(17,16), /* n */ + __BITS(3,0), /* m */ + __BITS(25,24), /* sel */ + __BIT(31), /* enable */ + SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), + SUNXI_CCU_DIV_GATE(H3_CLK_THS, "ths", ths_parents, THS_CLK_REG, /* reg */ __BITS(1,0), /* div */ @@ -400,6 +410,8 @@ static struct sunxi_ccu_clk sun8i_h3_ccu_clks[] = { __BIT(31), /* enable */ 0), + SUNXI_CCU_GATE(H3_CLK_BUS_CE, "bus-ce", "ahb1", + BUS_CLK_GATING_REG0, 5), SUNXI_CCU_GATE(H3_CLK_BUS_DMA, "bus-dma", "ahb1", BUS_CLK_GATING_REG0, 6), SUNXI_CCU_GATE(H3_CLK_BUS_MMC0, "bus-mmc0", "ahb1",