? sys/arch/sparc64/conf/GENERIC_NONSUN4V Index: sys/arch/sparc64/doc/TODO =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/doc/TODO,v retrieving revision 1.4 diff -u -r1.4 TODO --- sys/arch/sparc64/doc/TODO 5 Jun 2014 19:49:04 -0000 1.4 +++ sys/arch/sparc64/doc/TODO 7 Jun 2014 19:05:53 -0000 @@ -12,3 +12,4 @@ - locore.s: sun4v_datatrap missing implementation for trap levels 0 and 1 - pmap.c: pmap_calculate_colors() should known about sun4v - cpu.c: cpu_attach() does not emit cache info on sun4v +- check build without SUN4V defined Index: sys/arch/sparc64/include/cpu.h =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/include/cpu.h,v retrieving revision 1.110 diff -u -r1.110 cpu.h --- sys/arch/sparc64/include/cpu.h 21 Feb 2014 18:00:09 -0000 1.110 +++ sys/arch/sparc64/include/cpu.h 7 Jun 2014 19:05:54 -0000 @@ -180,6 +180,14 @@ */ paddr_t ci_mmfsa; + /* + * sun4v mondo control fields + */ + paddr_t ci_cpumq; /* cpu mondo queue address */ + paddr_t ci_devmq; /* device mondo queue address */ + paddr_t ci_cpuset; /* mondo recipient address */ + paddr_t ci_mondo; /* mondo message address */ + /* probe fault in PCI config space reads */ bool ci_pci_probe; bool ci_pci_fault; Index: sys/arch/sparc64/include/hypervisor.h =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/include/hypervisor.h,v retrieving revision 1.3 diff -u -r1.3 hypervisor.h --- sys/arch/sparc64/include/hypervisor.h 5 Jun 2014 18:36:44 -0000 1.3 +++ sys/arch/sparc64/include/hypervisor.h 7 Jun 2014 19:05:54 -0000 @@ -28,32 +28,40 @@ * API versioning */ +#ifndef _LOCORE int64_t hv_api_get_version(uint64_t api_group, uint64_t *major_number, uint64_t *minor_number); - +#endif /* * Domain services */ +#ifndef _LOCORE int64_t hv_mach_desc(paddr_t buffer, psize_t *length); +#endif /* * CPU services */ +#ifndef _LOCORE void hv_cpu_yield(void); int64_t hv_cpu_qconf(uint64_t queue, uint64_t base, uint64_t nentries); +#endif #define CPU_MONDO_QUEUE 0x3c #define DEVICE_MONDO_QUEUE 0x3d +#ifndef _LOCORE int64_t hv_cpu_mondo_send(uint64_t ncpus, paddr_t cpulist, paddr_t data); int64_t hv_cpu_myid(uint64_t *cpuid); +#endif /* * MMU services */ +#ifndef _LOCORE int64_t hv_mmu_demap_page(vaddr_t vaddr, uint64_t context, uint64_t flags); int64_t hv_mmu_demap_ctx(uint64_t context, uint64_t flags); int64_t hv_mmu_demap_all(uint64_t flags); @@ -62,10 +70,12 @@ int64_t hv_mmu_map_addr(vaddr_t vaddr, uint64_t context, uint64_t tte, uint64_t flags); int64_t hv_mmu_unmap_addr(vaddr_t vaddr, uint64_t context, uint64_t flags); +#endif #define MAP_DTLB 0x1 #define MAP_ITLB 0x2 +#ifndef _LOCORE struct tsb_desc { uint16_t td_idxpgsz; uint16_t td_assoc; @@ -78,18 +88,22 @@ int64_t hv_mmu_tsb_ctx0(uint64_t ntsb, paddr_t tsbptr); int64_t hv_mmu_tsb_ctxnon0(uint64_t ntsb, paddr_t tsbptr); +#endif /* * Cache and memory services */ +#ifndef _LOCORE int64_t hv_mem_scrub(paddr_t raddr, psize_t length); int64_t hv_mem_sync(paddr_t raddr, psize_t length); +#endif /* * Device interrupt services */ +#ifndef _LOCORE int64_t hv_intr_devino_to_sysino(uint64_t devhandle, uint64_t devino, uint64_t *sysino); int64_t hv_intr_getenabled(uint64_t sysino, uint64_t *intr_enabled); @@ -98,6 +112,7 @@ int64_t hv_intr_setstate(uint64_t sysino, uint64_t intr_state); int64_t hv_intr_gettarget(uint64_t sysino, uint64_t *cpuid); int64_t hv_intr_settarget(uint64_t sysino, uint64_t cpuid); +#endif #define INTR_DISABLED 0 #define INTR_ENABLED 1 @@ -106,6 +121,7 @@ #define INTR_RECEIVED 1 #define INTR_DELIVERED 2 +#ifndef _LOCORE int64_t hv_vintr_getcookie(uint64_t devhandle, uint64_t devino, uint64_t *cookie_value); int64_t hv_vintr_setcookie(uint64_t devhandle, uint64_t devino, @@ -122,21 +138,26 @@ uint64_t *cpuid); int64_t hv_vintr_settarget(uint64_t devhandle, uint64_t devino, uint64_t cpuid); +#endif /* * Time of day services */ +#ifndef _LOCORE int64_t hv_tod_get(uint64_t *tod); int64_t hv_tod_set(uint64_t tod); +#endif /* * Console services */ +#ifndef _LOCORE int64_t hv_cons_getchar(int64_t *ch); int64_t hv_cons_putchar(int64_t ch); int64_t hv_api_putchar(int64_t ch); +#endif #define CONS_BREAK -1 #define CONS_HUP -2 @@ -145,8 +166,10 @@ * Domain state services */ +#ifndef _LOCORE int64_t hv_soft_state_set(uint64_t software_state, paddr_t software_description_ptr); +#endif #define SIS_NORMAL 0x1 #define SIS_TRANSITION 0x2 @@ -155,6 +178,7 @@ * PCI I/O services */ +#ifndef _LOCORE int64_t hv_pci_iommu_map(uint64_t devhandle, uint64_t tsbid, uint64_t nttes, uint64_t io_attributes, paddr_t io_page_list_p, uint64_t *nttes_mapped); @@ -171,6 +195,7 @@ int64_t hv_pci_config_put(uint64_t devhandle, uint64_t pci_device, uint64_t pci_config_offset, uint64_t size, uint64_t data, uint64_t *error_flag); +#endif #define PCI_MAP_ATTR_READ 0x01 /* From memory */ #define PCI_MAP_ATTR_WRITE 0x02 /* To memory */ @@ -179,6 +204,7 @@ * PCI MSI services */ +#ifndef _LOCORE int64_t hv_pci_msiq_conf(uint64_t devhandle, uint64_t msiqid, uint64_t r_addr, uint64_t nentries); int64_t hv_pci_msiq_info(uint64_t devhandle, uint64_t msiqid, @@ -188,18 +214,22 @@ uint64_t *msiqvalid); int64_t hv_pci_msiq_setvalid(uint64_t devhandle, uint64_t msiqid, uint64_t msiqvalid); +#endif #define PCI_MSIQ_INVALID 0 #define PCI_MSIQ_VALID 1 +#ifndef _LOCORE int64_t hv_pci_msiq_getstate(uint64_t devhandle, uint64_t msiqid, uint64_t *msiqstate); int64_t hv_pci_msiq_setstate(uint64_t devhandle, uint64_t msiqid, uint64_t msiqstate); +#endif #define PCI_MSIQSTATE_IDLE 0 #define PCI_MSIQSTATE_ERROR 1 +#ifndef _LOCORE int64_t hv_pci_msiq_gethead(uint64_t devhandle, uint64_t msiqid, uint64_t *msiqhead); int64_t hv_pci_msiq_sethead(uint64_t devhandle, uint64_t msiqid, @@ -211,10 +241,12 @@ uint64_t *msivalidstate); int64_t hv_pci_msi_setvalid(uint64_t devhandle, uint64_t msinum, uint64_t msivalidstate); +#endif #define PCI_MSI_INVALID 0 #define PCI_MSI_VALID 1 +#ifndef _LOCORE int64_t hv_pci_msi_getmsiq(uint64_t devhandle, uint64_t msinum, uint64_t *msiqid); int64_t hv_pci_msi_setmsiq(uint64_t devhandle, uint64_t msinum, @@ -224,10 +256,12 @@ uint64_t *msistate); int64_t hv_pci_msi_setstate(uint64_t devhandle, uint64_t msinum, uint64_t msistate); +#endif #define PCI_MSISTATE_IDLE 0 #define PCI_MSISTATE_DELIVERED 1 +#ifndef _LOCORE int64_t hv_pci_msg_getmsiq(uint64_t devhandle, uint64_t msg, uint64_t *msiqid); int64_t hv_pci_msg_setmsiq(uint64_t devhandle, uint64_t msg, @@ -237,6 +271,7 @@ uint64_t *msgvalidstate); int64_t hv_pci_msg_setvalid(uint64_t devhandle, uint64_t msg, uint64_t msgvalidstate); +#endif #define PCIE_MSG_INVALID 0 #define PCIE_MSG_VALID 1 @@ -251,6 +286,7 @@ * Logical Domain Channel services */ +#ifndef _LOCORE int64_t hv_ldc_tx_qconf(uint64_t ldc_id, paddr_t base_raddr, uint64_t nentries); int64_t hv_ldc_tx_qinfo(uint64_t ldc_id, paddr_t *base_raddr, @@ -265,41 +301,50 @@ int64_t hv_ldc_rx_get_state(uint64_t ldc_id, uint64_t *head_offset, uint64_t *tail_offset, uint64_t *channel_state); int64_t hv_ldc_rx_set_qhead(uint64_t ldc_id, uint64_t head_offset); +#endif #define LDC_CHANNEL_DOWN 0 #define LDC_CHANNEL_UP 1 #define LDC_CHANNEL_RESET 2 +#ifndef _LOCORE int64_t hv_ldc_set_map_table(uint64_t ldc_id, paddr_t base_raddr, uint64_t nentries); int64_t hv_ldc_get_map_table(uint64_t ldc_id, paddr_t *base_raddr, uint64_t *nentries); int64_t hv_ldc_copy(uint64_t ldc_id, uint64_t flags, uint64_t cookie, paddr_t raddr, psize_t length, psize_t *ret_length); +#endif #define LDC_COPY_IN 0 #define LDC_COPY_OUT 1 +#ifndef _LOCORE int64_t hv_ldc_mapin(uint64_t ldc_id, uint64_t cookie, paddr_t *raddr, uint64_t *perms); int64_t hv_ldc_unmap(paddr_t raddr, uint64_t *perms); +#endif /* * Cryptographic services */ +#ifndef _LOCORE int64_t hv_rng_get_diag_control(void); int64_t hv_rng_ctl_read(paddr_t raddr, uint64_t *state, uint64_t *delta); int64_t hv_rng_ctl_write(paddr_t raddr, uint64_t state, uint64_t timeout, uint64_t *delta); +#endif #define RNG_STATE_UNCONFIGURED 0 #define RNG_STATE_CONFIGURED 1 #define RNG_STATE_HEALTHCHECK 2 #define RNG_STATE_ERROR 3 +#ifndef _LOCORE int64_t hv_rng_data_read_diag(paddr_t raddr, uint64_t size, uint64_t *delta); int64_t hv_rng_data_read(paddr_t raddr, uint64_t *delta); +#endif /* * Error codes Index: sys/arch/sparc64/include/trap.h =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/include/trap.h,v retrieving revision 1.9 diff -u -r1.9 trap.h --- sys/arch/sparc64/include/trap.h 27 Mar 2011 18:47:09 -0000 1.9 +++ sys/arch/sparc64/include/trap.h 7 Jun 2014 19:05:54 -0000 @@ -144,6 +144,14 @@ #define SYSCALL_G7RFLAG 0x800 /* use %g7 as above (deprecated) */ #define SYSCALL_G5RFLAG 0xc00 /* use %g5 as above (only ABI compatible way) */ +/* Software traps */ +#ifdef SUN4V +#define ST_FAST_TRAP 0x80 +#define ST_MMU_MAP_ADDR 0x83 +#define ST_MMU_UNMAP_ADDR 0x84 +#define ST_CORE_TRAP 0xff +#endif + /* * `software trap' macros to keep people happy (sparc v8 manual says not * to set the upper bits). Correct mask is 0xff for v9, but all values Index: sys/arch/sparc64/sparc64/cache.h =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/cache.h,v retrieving revision 1.22 diff -u -r1.22 cache.h --- sys/arch/sparc64/sparc64/cache.h 6 Jun 2011 02:49:39 -0000 1.22 +++ sys/arch/sparc64/sparc64/cache.h 7 Jun 2014 19:05:54 -0000 @@ -82,6 +82,9 @@ */ #include +#ifdef SUN4V +#include +#endif /* Various cache size/line sizes */ extern int ecache_min_line_size; @@ -117,13 +120,30 @@ void sp_tlb_flush_all_us(void); void sp_tlb_flush_all_usiii(void); +#ifdef SUN4V +static __inline__ void +sp_tlb_flush_pte_sun4v(vaddr_t va, int ctx) +{ + int64_t hv_rc; + hv_rc = hv_mmu_demap_page(va, ctx, MAP_DTLB|MAP_ITLB); + if ( hv_rc != H_EOK ) + panic("hv_mmu_demap_page(%p,%d) failed - rc = %" PRIx64 "\n", (void*)va, ctx, hv_rc); +} +#endif + static __inline__ void sp_tlb_flush_pte(vaddr_t va, int ctx) { - if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP()) - sp_tlb_flush_pte_usiii(va, ctx); + if (CPU_ISSUN4U || CPU_ISSUN4US) { + if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP()) + sp_tlb_flush_pte_usiii(va, ctx); + else + sp_tlb_flush_pte_us(va, ctx); + } +#ifdef SUN4V else - sp_tlb_flush_pte_us(va, ctx); + sp_tlb_flush_pte_sun4v(va, ctx); +#endif } static __inline__ void Index: sys/arch/sparc64/sparc64/cpu.c =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/cpu.c,v retrieving revision 1.111 diff -u -r1.111 cpu.c --- sys/arch/sparc64/sparc64/cpu.c 3 Jun 2014 20:01:34 -0000 1.111 +++ sys/arch/sparc64/sparc64/cpu.c 7 Jun 2014 19:05:54 -0000 @@ -78,6 +78,11 @@ #include #endif +#ifdef SUN4V +#define SUN4V_MONDO_QUEUE_SIZE 32 +#define SUN4V_QUEUE_ENTRY_SIZE 64 +#endif + int ecache_min_line_size; /* Linked list of all CPUs in system. */ @@ -135,6 +140,7 @@ id = prom_getpropint(cpu_node, "portid", -1); if (id == -1) id = prom_getpropint(cpu_node, "cpuid", -1); +#ifdef SUN4V if (CPU_ISSUN4V) { int reg[4]; int* regp=reg; @@ -146,6 +152,7 @@ /* cpuid in the lower 24 bits - sun4v hypervisor arch */ id = reg[0] & 0x0fffffff; } +#endif if (id == -1) panic("failed to determine cpuid"); @@ -347,6 +354,7 @@ } aprint_normal_dev(dev, ""); + /* XXX sun4v mising cache info printout */ bigcache = 0; icachesize = prom_getpropint(node, "icache-size", 0); @@ -441,6 +449,38 @@ */ uvm_page_recolor(atop(bigcache)); /* XXX */ + /* + * CPU specific ipi setup + * Currently only necessary for SUN4V + */ +#ifdef SUN4V + if (CPU_ISSUN4V) { + paddr_t pa = ci->ci_paddr; + int err; + + pa += CPUINFO_VA - INTSTACK; + pa += PAGE_SIZE; + + ci->ci_cpumq = pa; + err = hv_cpu_qconf(CPU_MONDO_QUEUE, ci->ci_cpumq, SUN4V_MONDO_QUEUE_SIZE); + if (err != H_EOK) + panic("Unable to set cpu mondo queue: %d", err); + pa += SUN4V_MONDO_QUEUE_SIZE * SUN4V_QUEUE_ENTRY_SIZE; + + ci->ci_devmq = pa; + err = hv_cpu_qconf(DEVICE_MONDO_QUEUE, ci->ci_devmq, SUN4V_MONDO_QUEUE_SIZE); + if (err != H_EOK) + panic("Unable to set device mondo queue: %d", err); + pa += SUN4V_MONDO_QUEUE_SIZE * SUN4V_QUEUE_ENTRY_SIZE; + + ci->ci_mondo = pa; + pa += 64; /* mondo message is 64 bytes */ + + ci->ci_cpuset = pa; + pa += 64; + } +#endif + } int Index: sys/arch/sparc64/sparc64/hvcall.S =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/hvcall.S,v retrieving revision 1.3 diff -u -r1.3 hvcall.S --- sys/arch/sparc64/sparc64/hvcall.S 8 Dec 2013 14:41:28 -0000 1.3 +++ sys/arch/sparc64/sparc64/hvcall.S 7 Jun 2014 19:05:54 -0000 @@ -18,11 +18,8 @@ */ #include - -#define FAST_TRAP 0x80 -#define MMU_MAP_ADDR 0x83 -#define MMU_UNMAP_ADDR 0x84 -#define CORE_TRAP 0xff +#include + #define MACH_EXIT 0x00 #define MACH_DESC 0x01 @@ -141,7 +138,7 @@ ENTRY(hv_api_putchar) mov API_PUTCHAR, %o5 - ta CORE_TRAP + ta ST_CORE_TRAP retl nop @@ -149,7 +146,7 @@ mov %o2, %o4 mov %o1, %o3 mov API_GET_VERSION, %o5 - ta CORE_TRAP + ta ST_CORE_TRAP stx %o1, [%o3] retl stx %o2, [%o4] @@ -158,44 +155,44 @@ mov %o1, %o2 ldx [%o2], %o1 mov MACH_DESC, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_cpu_yield) mov CPU_YIELD, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_cpu_qconf) mov CPU_QCONF, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_cpu_mondo_send) mov CPU_MONDO_SEND, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_cpu_myid) mov %o0, %o2 mov CPU_MYID, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_mmu_tsb_ctx0) mov MMU_TSB_CTX0, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_mmu_tsb_ctxnon0) mov MMU_TSB_CTXNON0, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop @@ -206,7 +203,7 @@ clr %o1 clr %o0 mov MMU_DEMAP_PAGE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop @@ -216,7 +213,7 @@ clr %o1 clr %o0 mov MMU_DEMAP_CTX, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop @@ -226,7 +223,7 @@ clr %o1 clr %o0 mov MMU_DEMAP_CTX, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop @@ -235,7 +232,7 @@ mov %o1, %o2 clr %o1 mov MMU_MAP_PERM_ADDR, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop @@ -243,188 +240,188 @@ mov %o1, %o2 clr %o1 mov MMU_UNMAP_PERM_ADDR, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_mmu_map_addr) - ta MMU_MAP_ADDR + ta ST_MMU_MAP_ADDR retl nop ENTRY(hv_mmu_unmap_addr) - ta MMU_UNMAP_ADDR + ta ST_MMU_UNMAP_ADDR retl nop ENTRY(hv_mem_scrub) mov MEM_SCRUB, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_mem_sync) mov MEM_SYNC, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_tod_get) mov %o0, %o2 mov TOD_GET, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_tod_set) mov TOD_SET, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_cons_getchar) mov %o0, %o2 mov CONS_GETCHAR, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_cons_putchar) mov CONS_PUTCHAR, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_soft_state_set) mov SOFT_STATE_SET, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_intr_devino_to_sysino) mov INTR_DEVINO2SYSINO, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_intr_getenabled) mov %o1, %o2 mov INTR_GETENABLED, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_intr_setenabled) mov INTR_SETENABLED, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_intr_getstate) mov %o1, %o2 mov INTR_GETSTATE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_intr_setstate) mov INTR_SETSTATE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_intr_gettarget) mov %o1, %o2 mov INTR_GETTARGET, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_intr_settarget) mov INTR_SETTARGET, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_vintr_getcookie) mov VINTR_GETCOOKIE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_vintr_setcookie) mov VINTR_SETCOOKIE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_vintr_getenabled) mov VINTR_GETENABLED, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_vintr_setenabled) mov VINTR_SETENABLED, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_vintr_getstate) mov VINTR_GETSTATE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_vintr_setstate) mov VINTR_SETSTATE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_vintr_gettarget) mov VINTR_GETTARGET, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_vintr_settarget) mov VINTR_SETTARGET, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_pci_iommu_map) mov %o5, %g5 mov PCI_IOMMU_MAP, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%g5] ENTRY(hv_pci_iommu_demap) mov PCI_IOMMU_DEMAP, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o3] ENTRY(hv_pci_iommu_getmap) mov %o2, %o4 mov PCI_IOMMU_GETMAP, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP stx %o1, [%o4] retl stx %o2, [%o3] ENTRY(hv_pci_iommu_getbypass) mov PCI_IOMMU_GETBYPASS, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o3] ENTRY(hv_pci_config_get) mov %o5, %g5 mov PCI_CONFIG_GET, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP stx %o1, [%o4] retl stx %o2, [%g5] @@ -432,129 +429,129 @@ ENTRY(hv_pci_config_put) mov %o5, %g5 mov PCI_CONFIG_PUT, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%g5] ENTRY(hv_pci_msiq_conf) mov PCI_MSIQ_CONF, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_pci_msiq_info) mov %o2, %o4 mov PCI_MSIQ_INFO, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP stx %o1, [%o4] retl stx %o2, [%o3] ENTRY(hv_pci_msiq_getvalid) mov PCI_MSIQ_GETVALID, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_pci_msiq_setvalid) mov PCI_MSIQ_SETVALID, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_pci_msiq_getstate) mov PCI_MSIQ_GETSTATE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_pci_msiq_setstate) mov PCI_MSIQ_SETSTATE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_pci_msiq_gethead) mov PCI_MSIQ_GETHEAD, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_pci_msiq_sethead) mov PCI_MSIQ_SETHEAD, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_pci_msiq_gettail) mov PCI_MSIQ_GETTAIL, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_pci_msi_getvalid) mov PCI_MSI_GETVALID, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_pci_msi_setvalid) mov PCI_MSI_SETVALID, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_pci_msi_getmsiq) mov PCI_MSI_GETMSIQ, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_pci_msi_setmsiq) mov PCI_MSI_SETMSIQ, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_pci_msi_getstate) mov PCI_MSI_GETSTATE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_pci_msi_setstate) mov PCI_MSI_SETSTATE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_pci_msg_getmsiq) mov PCI_MSG_GETMSIQ, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_pci_msg_setmsiq) mov PCI_MSG_SETMSIQ, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_pci_msg_getstate) mov PCI_MSG_GETSTATE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_pci_msg_setstate) mov PCI_MSG_SETSTATE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_ldc_tx_qconf) mov LDC_TX_QCONF, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop @@ -562,7 +559,7 @@ mov %o2, %o4 mov %o1, %o3 mov LDC_TX_QINFO, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP stx %o1, [%o3] retl stx %o2, [%o4] @@ -572,7 +569,7 @@ mov %o2, %g4 mov %o1, %o4 mov LDC_TX_GET_STATE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP stx %o1, [%o4] stx %o2, [%g4] retl @@ -580,13 +577,13 @@ ENTRY(hv_ldc_tx_set_qtail) mov LDC_TX_SET_QTAIL, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_ldc_rx_qconf) mov LDC_RX_QCONF, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop @@ -594,7 +591,7 @@ mov %o2, %o4 mov %o1, %o3 mov LDC_RX_QINFO, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP stx %o1, [%o3] retl stx %o2, [%o4] @@ -604,7 +601,7 @@ mov %o2, %g4 mov %o1, %o4 mov LDC_RX_GET_STATE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP stx %o1, [%o4] stx %o2, [%g4] retl @@ -612,13 +609,13 @@ ENTRY(hv_ldc_rx_set_qhead) mov LDC_RX_SET_QHEAD, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop ENTRY(hv_ldc_set_map_table) mov LDC_SET_MAP_TABLE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop @@ -626,7 +623,7 @@ mov %o2, %o4 mov %o1, %o3 mov LDC_GET_MAP_TABLE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP stx %o1, [%o3] retl stx %o2, [%o4] @@ -634,14 +631,14 @@ ENTRY(hv_ldc_copy) mov %o5, %g5 mov LDC_COPY, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%g5] ENTRY(hv_ldc_mapin) mov %o2, %o4 mov LDC_MAPIN, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP stx %o1, [%o4] retl stx %o2, [%o3] @@ -649,13 +646,13 @@ ENTRY(hv_ldc_unmap) mov %o1, %o2 mov LDC_UNMAP, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_rng_get_diag_control) mov RNG_GET_DIAG_CONTROL, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl nop @@ -663,26 +660,26 @@ mov %o2, %o4 mov %o1, %o3 mov RNG_CTL_READ, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP stx %o1, [%o3] retl stx %o2, [%o4] ENTRY(hv_rng_ctl_write) mov RNG_CTL_WRITE, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o3] ENTRY(hv_rng_data_read_diag) mov RNG_DATA_READ_DIAG, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] ENTRY(hv_rng_data_read) mov %o1, %o2 mov RNG_DATA_READ, %o5 - ta FAST_TRAP + ta ST_FAST_TRAP retl stx %o1, [%o2] Index: sys/arch/sparc64/sparc64/ipifuncs.c =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/ipifuncs.c,v retrieving revision 1.49 diff -u -r1.49 ipifuncs.c --- sys/arch/sparc64/sparc64/ipifuncs.c 19 May 2014 23:13:46 -0000 1.49 +++ sys/arch/sparc64/sparc64/ipifuncs.c 7 Jun 2014 19:05:54 -0000 @@ -53,6 +53,8 @@ #endif #endif +#define SPARC64_IPI_RETRIES 10000 + /* CPU sets containing halted, paused and resumed cpus */ static volatile sparc64_cpuset_t cpus_halted; static volatile sparc64_cpuset_t cpus_spinning; @@ -63,6 +65,11 @@ static int sparc64_ipi_wait(sparc64_cpuset_t volatile *, sparc64_cpuset_t); static void sparc64_ipi_error(const char *, sparc64_cpuset_t, sparc64_cpuset_t); +/* Send IPI functions for supported platforms */ +static void sparc64_send_ipi_sun4u(int, ipifunc_t, uint64_t, uint64_t); +#ifdef SUN4V +static void sparc64_send_ipi_sun4v(int, ipifunc_t, uint64_t, uint64_t); +#endif /* * These are the "function" entry points in locore.s/mp_subr.s to handle IPI's. @@ -71,6 +78,9 @@ void sparc64_ipi_pause(void *, void *); void sparc64_ipi_flush_pte_us(void *, void *); void sparc64_ipi_flush_pte_usiii(void *, void *); +#ifdef SUN4V +void sparc64_ipi_flush_pte_sun4v(void *, void *); +#endif void sparc64_ipi_dcache_flush_page_us(void *, void *); void sparc64_ipi_dcache_flush_page_usiii(void *, void *); void sparc64_ipi_blast_dcache(void *, void *); @@ -204,6 +214,21 @@ void sparc64_send_ipi(int upaid, ipifunc_t func, uint64_t arg1, uint64_t arg2) { +#ifdef SUN4V + if (CPU_ISSUN4V) + sparc64_send_ipi_sun4v(upaid, func, arg1, arg2); + else +#endif + sparc64_send_ipi_sun4u(upaid, func, arg1, arg2); + +} + +/* + * Send an interprocessor interrupt - sun4v. + */ +void +sparc64_send_ipi_sun4u(int upaid, ipifunc_t func, uint64_t arg1, uint64_t arg2) +{ int i, ik, shift = 0; uint64_t intr_func; @@ -261,6 +286,33 @@ " (tried %d times)", cpu_number(), upaid, i); } +#ifdef SUN4V +/* + * Send an interprocessor interrupt - sun4v. + */ +void +sparc64_send_ipi_sun4v(int cpuid, ipifunc_t func, uint64_t arg1, uint64_t arg2) +{ + struct cpu_info *ci = curcpu(); + int err, i; + + stha(ci->ci_cpuset, ASI_PHYS_CACHED, cpuid); + stxa(ci->ci_mondo, ASI_PHYS_CACHED, (vaddr_t)func); + stxa(ci->ci_mondo + 8, ASI_PHYS_CACHED, arg1); + stxa(ci->ci_mondo + 16, ASI_PHYS_CACHED, arg2); + + for (i = 0; i < SPARC64_IPI_RETRIES; i++) { + err = hv_cpu_mondo_send(1, ci->ci_cpuset, ci->ci_mondo); + if (err != H_EWOULDBLOCK) + break; + delay(10); + } + if (err != H_EOK) + panic("Unable to send mondo %lx to cpu %d: %d", + (long unsigned int)func, cpuid, err); +} +#endif + /* * Wait for IPI operation to complete. * Return 0 on success. @@ -394,8 +446,13 @@ int ctx; bool kpm = (pm == pmap_kernel()); ipifunc_t func; - +#ifdef SUN4V + if (CPU_ISSUN4V) + func = sparc64_ipi_flush_pte_sun4v; + else if (CPU_IS_USIII_UP()) +#else if (CPU_IS_USIII_UP()) +#endif func = sparc64_ipi_flush_pte_usiii; else func = sparc64_ipi_flush_pte_us; Index: sys/arch/sparc64/sparc64/mp_subr.S =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/mp_subr.S,v retrieving revision 1.5 diff -u -r1.5 mp_subr.S --- sys/arch/sparc64/sparc64/mp_subr.S 28 Apr 2013 23:42:24 -0000 1.5 +++ sys/arch/sparc64/sparc64/mp_subr.S 7 Jun 2014 19:05:54 -0000 @@ -78,7 +78,9 @@ #include #include #include - +#ifdef SUN4V +#include +#endif #include "ksyms.h" .register %g2,#scratch @@ -190,6 +192,21 @@ ba,a ret_from_intr_vector nop +#ifdef SUN4V +ENTRY(sparc64_ipi_flush_pte_sun4v) + mov %o0, %g1 ! save input + mov %o1, %g2 + mov %o2, %g4 + mov %g3, %o0 ! vaddr + mov %g5, %o1 ! ctx + mov MAP_DTLB|MAP_ITLB, %o2 ! flags + ta ST_MMU_UNMAP_ADDR + mov %g1, %o0 ! restore input + mov %g2, %o1 + mov %g4, %o2 + + retry +#endif /* * Secondary CPU bootstrap code.