WIP patches to try addressing support for the AR9485. Based on Stefan Sperling
patches.

 https://redmine.user.in-berlin.de/issues/216

Index: arn9003.c
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/arn9003.c,v
retrieving revision 1.6
diff -u -r1.6 arn9003.c
--- arn9003.c	23 Feb 2014 15:29:12 -0000	1.6
+++ arn9003.c	1 Feb 2015 21:06:30 -0000
@@ -66,8 +66,9 @@
 
 #define Static static
 
+Static void	ar9003_bb_watchdog_intr(struct athn_softc *);
 Static void	ar9003_calib_iq(struct athn_softc *);
-Static int	ar9003_calib_tx_iq(struct athn_softc *);
+Static int	ar9003_calib_tx_iq_result(struct athn_softc *);
 Static int	ar9003_compute_predistortion(struct athn_softc *,
 		    const uint32_t *, const uint32_t *);
 Static void	ar9003_disable_ofdm_weak_signal(struct athn_softc *);
@@ -221,6 +222,10 @@
 	sc->sc_obs_off = AR_OBS;
 	sc->sc_gpio_input_en_off = AR_GPIO_INPUT_EN_VAL;
 
+	sc->sc_workaround = AR_READ(sc, AR_WA) |
+	    AR_WA_ASPM_TIMER_BASED_DISABLE | AR_WA_D3_L1_DISABLE; 
+
+
 	if (!(sc->sc_flags & ATHN_FLAG_PCIE))
 		athn_config_nonpcie(sc);
 	else
@@ -588,6 +593,7 @@
 	AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
 	reg = AR_READ(sc, AR_GPIO_INPUT_MUX2);
 	reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);
+	reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, sc->sc_rfsilent_pin);
 	AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);
 	ar9003_gpio_config_input(sc, sc->sc_rfsilent_pin);
 	AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB);
@@ -1336,13 +1342,38 @@
 }
 #endif
 
+Static void
+ar9003_bb_watchdog_intr(struct athn_softc *sc)
+{
+	uint32_t status, reg;
+	static int phy_restart_disabled;
+
+	status = AR_READ(sc, AR_PHY_PANIC_WD_STATUS);
+	AR_WRITE(sc, AR_PHY_PANIC_WD_STATUS,
+	    status & ~AR_PHY_PANIC_WD_STATUS_CLR);
+
+	if (!phy_restart_disabled &&
+	    MS(status, AR_PHY_PANIC_WD_RX_OFDM) == 0xb) {
+		/* BB received unsupported frame rate and will hang
+		 * if the PHY is restarted. Disable PHY restart. */
+		reg = AR_READ(sc, AR_PHY_RESTART);
+		reg &= ~AR_PHY_RESTART_ENA;
+		AR_WRITE(sc, AR_PHY_RESTART, reg);
+		phy_restart_disabled = 1;
+	}
+}
+
+
 Static int
 ar9003_intr(struct athn_softc *sc)
 {
 	uint32_t intr, sync;
+	static int count;
 
 	/* Get pending interrupts. */
 	intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE);
+	if (count < 20)
+		printf("%s: AR_INTR_ASYNC_CAUSE=0x%x\n", __func__, intr);
 	if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) {
 		intr = AR_READ(sc, AR_INTR_SYNC_CAUSE);
 		if (intr == AR_INTR_SPURIOUS || (intr & sc->sc_isync) == 0)
@@ -1350,29 +1381,37 @@
 	}
 
 	if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
-	    (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
+	    (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) {
 		intr = AR_READ(sc, AR_ISR);
-	else
+		if (count < 20)
+			printf("%s: AR_ISR=0x%x\n", __func__, intr);
+	} else
 		intr = 0;
 	sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync;
+	if (count < 20)
+		printf("%s: AR_INTR_SYNC_CAUSE=0x%x\n", __func__, sync);
 	if (intr == 0 && sync == 0)
 		return 0;	/* Not for us. */
 
 	if (intr != 0) {
 		if (intr & AR_ISR_BCNMISC) {
 			uint32_t intr2 = AR_READ(sc, AR_ISR_S2);
+			if (count < 20)
+				printf("%s: AR_ISR_S2=0x%x\n", __func__, intr2);
 #ifdef notyet
 			if (intr2 & AR_ISR_S2_TIM)
 				/* TBD */;
 			if (intr2 & AR_ISR_S2_TSFOOR)
 				/* TBD */;
-			if (intr2 & AR_ISR_S2_BB_WATCHDOG)
-				/* TBD */;
 #else
+			if (intr2 & AR_ISR_S2_BB_WATCHDOG)
+				ar9003_bb_watchdog_intr(sc);
 			__USE(intr2);
 #endif
 		}
 		intr = AR_READ(sc, AR_ISR_RAC);
+		if (count < 20)
+			printf("%s: AR_ISR_RAC=0x%x\n", __func__, intr);
 		if (intr == AR_INTR_SPURIOUS)
 			return 1;
 
@@ -1404,6 +1443,7 @@
 #endif
 		}
 	}
+	count++;
 	if (sync != 0) {
 		if (sync & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
 			AR_WRITE(sc, AR_RC, AR_RC_HOSTIF);
@@ -2132,30 +2172,68 @@
 	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
 }
 
+#define DELPT	32
 PUBLIC int
 ar9003_init_calib(struct athn_softc *sc)
 {
 	uint8_t txchainmask, rxchainmask;
 	uint32_t reg;
-	int ntries;
+	int ntries, error;
 
 	/* Save chains masks. */
 	txchainmask = sc->sc_txchainmask;
 	rxchainmask = sc->sc_rxchainmask;
 	/* Configure hardware before calibration. */
-	if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_CHAIN2_DISABLE)
-		txchainmask = rxchainmask = 0x3;
-	else
-		txchainmask = rxchainmask = 0x7;
+	if (!AR_SREV_9485_OR_LATER(sc)) {
+		if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_CHAIN2_DISABLE)
+			txchainmask = rxchainmask = 0x3;
+		else
+			txchainmask = rxchainmask = 0x7;
+	}
 	ar9003_init_chains(sc);
 
 	/* Perform Tx IQ calibration. */
-	ar9003_calib_tx_iq(sc);
-	/* Disable and re-enable the PHY chips. */
-	AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
-	AR_WRITE_BARRIER(sc);
-	DELAY(5);
-	AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+	reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1);
+	reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);
+	AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg);
+
+	/* 
+	 * For AR9485 or later chips, Tx IQ cal runs as part of
+	 * AGC calibration.
+	 */
+	if (AR_SREV_9485_OR_LATER(sc)) {
+		AR_SETBITS(sc, AR_PHY_TX_IQCAL_CONTROL_0,
+		    AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
+
+		/* Disable calibrations we don't (yet?) support. */
+		AR_CLRBITS(sc, AR_PHY_AGC_CONTROL,
+		   AR_PHY_AGC_CONTROL_OFFSET_CAL |
+		   AR_PHY_AGC_CONTROL_FLTR_CAL |
+		   AR_PHY_AGC_CONTROL_PKDET_CAL);
+	} else {
+		/* Start Tx IQ calibration. */
+		AR_SETBITS(sc, AR_PHY_TX_IQCAL_START,
+		    AR_PHY_TX_IQCAL_START_DO_CAL);
+		/* Wait for completion. */
+		for (ntries = 0; ntries < 10000; ntries++) {
+			reg = AR_READ(sc, AR_PHY_TX_IQCAL_START);
+			if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL))
+				break;
+			DELAY(10);
+		}
+		if (ntries == 10000)
+			return (ETIMEDOUT);
+
+		error = ar9003_calib_tx_iq_result(sc);
+		if (error)
+			return (error);
+
+		/* Disable and re-enable the PHY chips. */
+		AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
+		AR_WRITE_BARRIER(sc);
+		DELAY(5);
+		AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+	}
 
 	/* Calibrate the AGC. */
 	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
@@ -2169,6 +2247,12 @@
 	if (ntries == 10000)
 		return ETIMEDOUT;
 
+	if (AR_SREV_9485_OR_LATER(sc)) {
+		error = ar9003_calib_tx_iq_result(sc);
+		if (error)
+			return (error);
+	}
+
 	/* Restore chains masks. */
 	sc->sc_txchainmask = txchainmask;
 	sc->sc_rxchainmask = rxchainmask;
@@ -2277,7 +2361,6 @@
 	memset(&sc->sc_calib, 0, sizeof(sc->sc_calib));
 }
 
-#define DELPT	32
 Static int
 ar9003_get_iq_corr(struct athn_softc *sc, int32_t res[6], int32_t coeff[2])
 {
@@ -2399,27 +2482,11 @@
 }
 
 Static int
-ar9003_calib_tx_iq(struct athn_softc *sc)
+ar9003_calib_tx_iq_result(struct athn_softc *sc)
 {
 	uint32_t reg;
 	int32_t res[6], coeff[2];
-	int i, j, ntries;
-
-	reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1);
-	reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);
-	AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg);
-
-	/* Start Tx IQ calibration. */
-	AR_SETBITS(sc, AR_PHY_TX_IQCAL_START, AR_PHY_TX_IQCAL_START_DO_CAL);
-	/* Wait for completion. */
-	for (ntries = 0; ntries < 10000; ntries++) {
-		reg = AR_READ(sc, AR_PHY_TX_IQCAL_START);
-		if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL))
-			break;
-		DELAY(10);
-	}
-	if (ntries == 10000)
-		return ETIMEDOUT;
+	int i, j;
 
 	for (i = 0; i < sc->sc_ntxchains; i++) {
 		/* Read Tx IQ calibration status for this chain. */
@@ -2428,7 +2495,7 @@
 			return EIO;
 		/*
 		 * Read Tx IQ calibration results for this chain.
-		 * This consists in twelve signed 12-bit values.
+		 * Results consist of twelve signed 12-bit values.
 		 */
 		for (j = 0; j < 3; j++) {
 			AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY,
@@ -3264,6 +3331,23 @@
 	ar9003_set_phy(sc, c, extc);
 	ar9003_init_chains(sc);
 
+	if (AR_SREV_9380_20_OR_LATER(sc)) {
+		/* Enable BB watchdog interrupt. */
+		reg = AR_READ(sc, AR_PHY_PANIC_WD_CTL_2);
+		reg |= AR_PHY_PANIC_WD_IRQ_ENABLE;
+		reg &= ~AR_PHY_PANIC_WD_RST_ENABLE;
+		AR_WRITE(sc, AR_PHY_PANIC_WD_CTL_2, reg);
+
+		/*
+		 * Enable watchdog in non-IDLE mode, disable in IDLE mode,
+		 * set idle timeout to 25ms.
+		 */
+		AR_WRITE(sc, AR_PHY_PANIC_WD_CTL_1,
+		    AR_PHY_PANIC_WD_NON_IDLE_ENABLE |
+		    AR_PHY_PANIC_WD_IDLE_MASK |
+		    ((AR_PHY_PANIC_WD_NON_IDLE_MASK) & ((100 * 25) / 74) << 2));
+	}
+
 	ops->set_txpower(sc, c, extc);
 #undef X
 }
@@ -3446,3 +3530,45 @@
 	AR_WRITE(sc, AR_PHY_TIMING5, reg);
 	AR_WRITE_BARRIER(sc);
 }
+
+
+PUBLIC void
+ar9003_init_pll(struct athn_softc *sc)
+{
+	uint32_t reg;
+
+	if (AR_SREV_9485(sc)) {
+		reg = AR_READ(sc, AR_PHY_65NM_CH0_DPLL2);
+		reg = RW(reg, AR_PHY_65NM_CH0_DPLL2_PLL_PWD, 0x01);
+		AR_WRITE(sc, AR_PHY_65NM_CH0_DPLL2, reg);
+
+		/* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
+		reg = RW(reg, AR_PHY_65NM_CH0_DPLL2_KD, 0x40);
+		reg = RW(reg, AR_PHY_65NM_CH0_DPLL2_KI, 0x04);
+		AR_WRITE(sc, AR_PHY_65NM_CH0_DPLL2, reg);
+
+		reg = AR_READ(sc, AR_PHY_65NM_CH0_DPLL1);
+		reg = RW(reg, AR_PHY_65NM_CH0_DPLL1_REFDIV, 0x05);
+		reg = RW(reg, AR_PHY_65NM_CH0_DPLL1_NINI, 0x58);
+		reg = RW(reg, AR_PHY_65NM_CH0_DPLL1_NFRAC, 0x00);
+		AR_WRITE(sc, AR_PHY_65NM_CH0_DPLL1, reg);
+
+		reg = AR_READ(sc, AR_PHY_65NM_CH0_DPLL2);
+		reg = RW(reg, AR_PHY_65NM_CH0_DPLL2_OUTDIV, 0x01);
+		reg = RW(reg, AR_PHY_65NM_CH0_DPLL2_LOCAL_PLL, 0x01);
+		reg = RW(reg, AR_PHY_65NM_CH0_DPLL2_NEGTRIG, 0x01);
+		AR_WRITE(sc, AR_PHY_65NM_CH0_DPLL2, reg);
+
+		/* program BB PLL phase_shift to 0x6 */
+		reg = AR_READ(sc, AR_PHY_65NM_CH0_DPLL3);
+		reg = RW(reg, AR_PHY_65NM_CH0_DPLL3_PHASE_SHIFT, 0x06);
+		AR_WRITE(sc, AR_PHY_65NM_CH0_DPLL3, reg);
+		
+		reg = AR_READ(sc, AR_PHY_65NM_CH0_DPLL2);
+		reg = RW(reg, AR_PHY_65NM_CH0_DPLL2_PLL_PWD, 0x00);
+		AR_WRITE(sc, AR_PHY_65NM_CH0_DPLL2, reg);
+
+		AR_WRITE_BARRIER(sc);
+		DELAY(1000);
+	}
+}
Index: arn9003.h
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/arn9003.h,v
retrieving revision 1.1
diff -u -r1.1 arn9003.h
--- arn9003.h	30 Mar 2013 02:53:01 -0000	1.1
+++ arn9003.h	1 Feb 2015 21:06:30 -0000
@@ -30,6 +30,7 @@
 
 int	ar9003_attach(struct athn_softc *);
 int	ar9003_init_calib(struct athn_softc *);
+void	ar9003_init_pll(struct athn_softc *);
 void	ar9003_reset_txsring(struct athn_softc *);
 void	ar9003_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *,
 	    uint8_t, const uint8_t *, const struct ar_cal_target_power_leg *,
Index: arn9003reg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/arn9003reg.h,v
retrieving revision 1.1
diff -u -r1.1 arn9003reg.h
--- arn9003reg.h	30 Mar 2013 02:53:01 -0000	1.1
+++ arn9003reg.h	1 Feb 2015 21:06:32 -0000
@@ -202,18 +202,27 @@
 #define AR_PHY_TX_FORCED_GAIN		0x0a458
 #define AR_PHY_PDADC_TAB(i)		(0x0a480 + (i) * 0x1000)
 #define AR_PHY_TXGAIN_TABLE(i)		(0x0a500 + (i) * 4)
-#define AR_PHY_TX_IQCAL_CONTROL_1	0x0a648
-#define AR_PHY_TX_IQCAL_START		0x0a640
+#define AR_PHY_TX_IQCAL_CONTROL_0   	(AR_SREV_9485(sc) ? 0x0a5c4 : 0x0a644)
+#define AR_PHY_TX_IQCAL_CONTROL_1	(AR_SREV_9485(sc) ? 0x0a5c8 : 0x0a648)
+#define AR_PHY_TX_IQCAL_START		(AR_SREV_9485(sc) ? 0x0a5c4 : 0x0a640)
 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i)	\
-					(0x0a650 + (i) * 0x1000)
-#define AR_PHY_TX_IQCAL_STATUS_B(i)	(0x0a68c + (i) * 0x1000)
-#define AR_PHY_PAPRD_TRAINER_CNTL1	0x0a690
-#define AR_PHY_PAPRD_TRAINER_CNTL2	0x0a694
-#define AR_PHY_PAPRD_TRAINER_CNTL3	0x0a698
-#define AR_PHY_PAPRD_TRAINER_CNTL4	0x0a69c
-#define AR_PHY_PAPRD_TRAINER_STAT1	0x0a6a0
-#define AR_PHY_PAPRD_TRAINER_STAT2	0x0a6a4
-#define AR_PHY_PAPRD_TRAINER_STAT3	0x0a6a8
+					(((i) == 0) \
+					    ? AR_SREV_9485(sc) \
+					        ? (0x0a5d0 + (i) * 0x1000) \
+					        : (0x0a650 + (i) * 0x1000) \
+					    : (0x0a650 + (i) * 0x1000))
+#define AR_PHY_TX_IQCAL_STATUS_B(i)	(((i) == 0) \
+					    ? AR_SREV_9485(sc) \
+					        ? (0x0a5f0 + (i) * 0x1000) \
+					        : (0x0a68c + (i) * 0x1000) \
+					    : (0x0a68c + (i) * 0x1000))
+#define AR_PHY_PAPRD_TRAINER_CNTL1	(AR_SREV_9485(sc) ? 0xa780 : 0x0a690)
+#define AR_PHY_PAPRD_TRAINER_CNTL2	(AR_SREV_9485(sc) ? 0xa784 : 0x0a694)
+#define AR_PHY_PAPRD_TRAINER_CNTL3	(AR_SREV_9485(sc) ? 0xa788 : 0x0a698)
+#define AR_PHY_PAPRD_TRAINER_CNTL4	(AR_SREV_9485(sc) ? 0xa78c : 0x0a69c)
+#define AR_PHY_PAPRD_TRAINER_STAT1	(AR_SREV_9485(sc) ? 0xa790 : 0x0a6a0)
+#define AR_PHY_PAPRD_TRAINER_STAT2	(AR_SREV_9485(sc) ? 0xa794 : 0x0a6a4)
+#define AR_PHY_PAPRD_TRAINER_STAT3	(AR_SREV_9485(sc) ? 0xa798 : 0x0a6a8)
 #define AR_PHY_PANIC_WD_STATUS		0x0a7c0
 #define AR_PHY_PANIC_WD_CTL_1		0x0a7c4
 #define AR_PHY_PANIC_WD_CTL_2		0x0a7c8
@@ -222,6 +231,39 @@
 #define AR_PHY_ONLY_CTL			0x0a7d4
 #define AR_PHY_ECO_CTRL			0x0a7dc
 
+/* Bits for AR_PHY_PANIC_WD_STATUS. */
+#define AR_PHY_PANIC_WD_STATUS_CLR	0x00000008	
+#define AR_PHY_PANIC_WD_INFO		0x00000007
+#define AR_PHY_PANIC_WD_INFO_S		0
+#define AR_PHY_PANIC_WD_DET_HANG	0x00000008
+#define AR_PHY_PANIC_WD_DET_HANG_S	3
+#define AR_PHY_PANIC_WD_RADAR_M		0x000000f0
+#define AR_PHY_PANIC_WD_RADAR_S		4
+#define AR_PHY_PANIC_WD_RX_OFDM_M	0x00000f00
+#define AR_PHY_PANIC_WD_RX_OFDM_S	8
+#define AR_PHY_PANIC_WD_RX_CCK_M	0x0000f000
+#define AR_PHY_PANIC_WD_RX_CCK_S	12
+#define AR_PHY_PANIC_WD_TX_OFDM_M	0x000f0000
+#define AR_PHY_PANIC_WD_TX_OFDM_S	16
+#define AR_PHY_PANIC_WD_TX_CCK_M	0x00f00000
+#define AR_PHY_PANIC_WD_TX_CCK_S	20
+#define AR_PHY_PANIC_WD_AGC_M		0x0f000000
+#define AR_PHY_PANIC_WD_AGC_S		24
+#define AR_PHY_PANIC_WD_SRCH_M		0Xf0000000
+#define AR_PHY_PANIC_WD_SRCH_S		28
+
+
+/* Bits for AR_PHY_PANIC_WD_CTL_1. */
+#define AR_PHY_PANIC_WD_NON_IDLE_ENABLE	0x00000001
+#define AR_PHY_PANIC_WD_IDLE_ENABLE	0x00000002
+#define AR_PHY_PANIC_WD_IDLE_MASK	0Xffff0000
+#define AR_PHY_PANIC_WD_NON_IDLE_MASK	0x0000fffc
+
+/* Bits for AR_PHY_PANIC_WD_CTL_2. */
+#define AR_PHY_PANIC_WD_RST_ENABLE	0x00000002
+#define AR_PHY_PANIC_WD_IRQ_ENABLE	0x00000004
+#define AR_PHY_PANIC_WD_CNTL2_MASK	0Xfffffff9
+
 /*
  * Analog registers.
  */
@@ -234,9 +276,12 @@
 #define AR_PHY_65NM_CH0_RXTX1		0x16100
 #define AR_PHY_65NM_CH0_RXTX2		0x16104
 #define AR_PHY_65NM_CH0_RXTX4		0x1610c
+#define AR_PHY_65NM_CH0_DPLL1		0x16180
+#define AR_PHY_65NM_CH0_DPLL2		0x16184
+#define AR_PHY_65NM_CH0_DPLL3		0x16188
 #define AR9485_PHY_65NM_CH0_TOP2	0x16284
 #define AR_PHY_65NM_CH0_TOP		0x16288
-#define AR_PHY_65NM_CH0_THERM		0x16290
+#define AR_PHY_65NM_CH0_THERM		(AR_SREV_9485(sc) ? 0x1628c : 0x16290)
 #define AR9485_PHY_CH0_XTAL		0x16290
 #define AR_PHY_65NM_CH1_RXTX1		0x16500
 #define AR_PHY_65NM_CH1_RXTX2		0x16504
@@ -624,6 +669,7 @@
 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF		0x00020000
 #define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS	0x00040000
 #define AR_PHY_AGC_CONTROL_CLC_SUCCESS		0x00080000
+#define AR_PHY_AGC_CONTROL_PKDET_CAL		0x00100000
 
 /* Bits for AR_PHY_CALMODE. */
 #define AR_PHY_CALMODE_IQ		0x00000000
@@ -769,6 +815,9 @@
 #define AR_PHY_TXGAIN_INDEX_M		0xff000000
 #define AR_PHY_TXGAIN_INDEX_S		24
 
+/* Bits for AR_PHY_TX_IQCAL_CONTROL_0. */
+#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL		0x80000000
+
 /* Bits for AR_PHY_TX_IQCAL_CONTROL_1. */
 #define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_M	0x01fc0000
 #define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S	18
@@ -891,6 +940,32 @@
 /* Bits for AR_PHY_65NM_CH0_RXTX4. */
 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON  0x10000000
 
+/* Bits for AR_PHY_65NM_CH0_DPLL1. */
+#define AR_PHY_65NM_CH0_DPLL1_REFDIV_M	0xf8000000
+#define AR_PHY_65NM_CH0_DPLL1_REFDIV_S	27
+#define AR_PHY_65NM_CH0_DPLL1_NINI_M	0X07fc0000
+#define AR_PHY_65NM_CH0_DPLL1_NINI_S	18
+#define AR_PHY_65NM_CH0_DPLL1_NFRAC_M	0X0003ffff
+#define AR_PHY_65NM_CH0_DPLL1_NFRAC_S	0
+
+/* Bits for AR_PHY_65NM_CH0_DPLL2. */
+#define AR_PHY_65NM_CH0_DPLL2_LOCAL_PLL_M	0x40000000
+#define AR_PHY_65NM_CH0_DPLL2_LOCAL_PLL_S	30
+#define AR_PHY_65NM_CH0_DPLL2_KI_M		0x3c000000
+#define AR_PHY_65NM_CH0_DPLL2_KI_S		26
+#define AR_PHY_65NM_CH0_DPLL2_KD_M		0x03f80000
+#define AR_PHY_65NM_CH0_DPLL2_KD_S		19
+#define AR_PHY_65NM_CH0_DPLL2_NEGTRIG_M		0x00040000
+#define AR_PHY_65NM_CH0_DPLL2_NEGTRIG_S		18
+#define AR_PHY_65NM_CH0_DPLL2_PLL_PWD_M		0x00010000
+#define AR_PHY_65NM_CH0_DPLL2_PLL_PWD_S		16
+#define AR_PHY_65NM_CH0_DPLL2_OUTDIV_M		0x0000e000
+#define AR_PHY_65NM_CH0_DPLL2_OUTDIV_S		13
+
+/* Bits for AR_PHY_65NM_CH0_DPLL3. */
+#define AR_PHY_65NM_CH0_DPLL3_PHASE_SHIFT_M	0x3f800000
+#define AR_PHY_65NM_CH0_DPLL3_PHASE_SHIFT_S	23
+
 /* Bits for AR9485_PHY_65NM_CH0_TOP2. */
 #define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_M	0x0000f000
 #define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_S	12
@@ -934,7 +1009,6 @@
 #define AR_OTP_STATUS_ACCESS_BUSY	0x2
 #define AR_OTP_STATUS_VALID		0x4
 
-
 #define AR9003_MAX_CHAINS	3
 
 #define AR9003_TX_QDEPTH	8
Index: arn9380.c
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/arn9380.c,v
retrieving revision 1.3
diff -u -r1.3 arn9380.c
--- arn9380.c	22 Jan 2014 17:29:29 -0000	1.3
+++ arn9380.c	1 Feb 2015 21:06:33 -0000
@@ -222,7 +222,7 @@
 	struct ar9380_eeprom *eep = sc->sc_eep;
 	struct ar9380_base_eep_hdr *base = &eep->baseEepHeader;
 	struct ar9380_modal_eep_header *modal;
-	int i;
+	int i, maxchains;
 
 	base->regDmn[0] = bswap16(base->regDmn[0]);
 	base->regDmn[1] = bswap16(base->regDmn[1]);
@@ -233,7 +233,8 @@
 	modal->antCtrlCommon2 = bswap32(modal->antCtrlCommon2);
 	modal->papdRateMaskHt20 = bswap32(modal->papdRateMaskHt20);
 	modal->papdRateMaskHt40 = bswap32(modal->papdRateMaskHt40);
-	for (i = 0; i < AR9380_MAX_CHAINS; i++)
+	maxchains = AR_SREV_9485(sc) ? 1 : AR9380_MAX_CHAINS;
+	for (i = 0; i < maxchains; i++)
 		modal->antCtrlChain[i] = bswap16(modal->antCtrlChain[i]);
 
 	modal = &eep->modalHeader5G;
@@ -241,7 +242,7 @@
 	modal->antCtrlCommon2 = bswap32(modal->antCtrlCommon2);
 	modal->papdRateMaskHt20 = bswap32(modal->papdRateMaskHt20);
 	modal->papdRateMaskHt40 = bswap32(modal->papdRateMaskHt40);
-	for (i = 0; i < AR9380_MAX_CHAINS; i++)
+	for (i = 0; i < maxchains; i++)
 		modal->antCtrlChain[i] = bswap16(modal->antCtrlChain[i]);
 #endif
 }
@@ -266,13 +267,17 @@
     struct ieee80211_channel *extc)
 {
 	uint32_t freq = c->ic_freq;
-	uint32_t chansel, phy;
+	uint32_t chansel, chanfrac, phy;
 
 	if (IEEE80211_IS_CHAN_2GHZ(c)) {
-		if (AR_SREV_9485(sc))
-			chansel = ((freq << 16) - 215) / 15;
-		else
+		if (AR_SREV_9485(sc)) {
+			chansel = (freq * 4) / 120;
+			chanfrac = (((freq * 4) % 120) * 0x20000) / 120;
+			chansel = (chansel << 17) | (chanfrac);
+		} else {
+			/* XXX not valid for >= AR_SREV_9330 */
 			chansel = (freq << 16) / 15;
+		}
 		AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, AR9380_BMODE);
 	}
 	else {
@@ -867,7 +872,7 @@
 	const struct ar9380_modal_eep_header *modal;
 	uint32_t reg;
 	int8_t slope;
-	int i, corr, temp, temp0;
+	int i, corr, temp, temp0, maxchains;
 
 	if (IEEE80211_IS_CHAN_2GHZ(c))
 		modal = &eep->modalHeader2G;
@@ -875,7 +880,8 @@
 		modal = &eep->modalHeader5G;
 
 	temp0 = 0;	/* XXX: gcc */
-	for (i = 0; i < AR9380_MAX_CHAINS; i++) {
+	maxchains = AR_SREV_9485(sc) ? 1 : AR9380_MAX_CHAINS;
+	for (i = 0; i < maxchains; i++) {
 		ar9380_get_correction(sc, c, i, &corr, &temp);
 		if (i == 0)
 			temp0 = temp;
Index: athn.c
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/athn.c,v
retrieving revision 1.10
diff -u -r1.10 athn.c
--- athn.c	24 Jul 2014 19:47:15 -0000	1.10
+++ athn.c	1 Feb 2015 21:06:35 -0000
@@ -71,6 +71,7 @@
 #include <dev/ic/arn9280.h>
 #include <dev/ic/arn9285.h>
 #include <dev/ic/arn9287.h>
+#include <dev/ic/arn9003.h>
 #include <dev/ic/arn9380.h>
 
 #define Static static
@@ -79,7 +80,7 @@
 	(((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING))
 
 #ifdef ATHN_DEBUG
-int athn_debug = 0;
+int athn_debug = DBG_ALL;
 #endif
 
 Static int	athn_clock_rate(struct athn_softc *);
@@ -740,8 +741,7 @@
 	uint32_t pll;
 
 	if (AR_SREV_9380_10_OR_LATER(sc)) {
-		if (AR_SREV_9485(sc))
-			AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666);
+		ar9003_init_pll(sc);
 		pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5);
 		pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);
 	}
@@ -774,6 +774,10 @@
 	}
 	DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n", pll);
 	AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll);
+
+	if (AR_SREV_9485(sc))
+		DELAY(1000);
+
 	if (AR_SREV_9271(sc)) {
 		/* Switch core clock to 117MHz. */
 		AR_WRITE_BARRIER(sc);
@@ -2301,7 +2305,7 @@
 	/* Initialize interrupt mask. */
 	sc->sc_imask =
 	    AR_IMR_TXDESC | AR_IMR_TXEOL |
-	    AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN |
+	    AR_IMR_RXERR | AR_IMR_RXORN |
 	    AR_IMR_RXMINTR | AR_IMR_RXINTM |
 	    AR_IMR_GENTMR | AR_IMR_BCNMISC;
 	if (AR_SREV_9380_10_OR_LATER(sc))
@@ -2346,8 +2350,8 @@
 	ops->init_baseband(sc);
 
 	if ((error = athn_init_calib(sc, curchan, extchan)) != 0) {
-		aprint_error_dev(sc->sc_dev,
-		    "could not initialize calibration\n");
+		aprint_error_dev(sc->sc_dev, "could not initialize calibration (error %d)\n",
+		    error);
 		return error;
 	}
 
Index: athnreg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/athnreg.h,v
retrieving revision 1.1
diff -u -r1.1 athnreg.h
--- athnreg.h	30 Mar 2013 02:53:02 -0000	1.1
+++ athnreg.h	1 Feb 2015 21:06:37 -0000
@@ -257,7 +257,7 @@
 
 
 /* Bits for AR_CR. */
-#define AR_CR_RXE	0x00000004
+#define AR_CR_RXE	(AR_SREV_9380_20_OR_LATER(sc) ? 0x000c : 0x0004)
 #define AR_CR_RXD	0x00000020
 #define AR_CR_SWI	0x00000040
 
@@ -726,10 +726,12 @@
 #define AR5416_WA_DEFAULT	0x0000073f
 #define AR9280_WA_DEFAULT	0x0040073b
 #define AR9285_WA_DEFAULT	0x004a050b
-#define AR_WA_UNTIE_RESET_EN	0x00008000
-#define AR_WA_RESET_EN		0x00040000
-#define AR_WA_ANALOG_SHIFT	0x00100000
-#define AR_WA_POR_SHORT		0x00200000
+#define AR_WA_ASPM_TIMER_BASED_DISABLE 	0x00002000
+#define AR_WA_D3_L1_DISABLE		0x00004000
+#define AR_WA_UNTIE_RESET_EN		0x00008000
+#define AR_WA_RESET_EN			0x00040000
+#define AR_WA_ANALOG_SHIFT		0x00100000
+#define AR_WA_POR_SHORT			0x00200000
 
 /* Bits for AR_PM_STATE. */
 #define AR_PM_STATE_PME_D3COLD_VAUX	0x00100000
@@ -1418,7 +1420,9 @@
 	 (AR_SREV_9380(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9380_20))
 
 #define AR_SREV_9485(sc) \
-	((sc)->sc_mac_ver == AR_SREV_VERSION_9485)
+ 	((sc)->sc_mac_ver == AR_SREV_VERSION_9485)
+#define AR_SREV_9485_OR_LATER(sc) \
+	((sc)->sc_mac_ver >= AR_SREV_VERSION_9485)
 
 #define AR_SINGLE_CHIP(sc)	AR_SREV_9280_10_OR_LATER(sc)
 
Index: athnvar.h
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/athnvar.h,v
retrieving revision 1.4
diff -u -r1.4 athnvar.h
--- athnvar.h	6 Apr 2013 16:50:48 -0000	1.4
+++ athnvar.h	1 Feb 2015 21:06:37 -0000
@@ -35,6 +35,8 @@
 #define ATHN_SOFTC(sc)		((struct athn_softc *)(sc))
 #define ATHN_NODE(ni)		((struct athn_node *)(ni))
 
+#define ATHN_DEBUG
+
 #ifdef ATHN_DEBUG
 #define	DBG_INIT	__BIT(0)
 #define	DBG_FN		__BIT(1)
@@ -628,8 +630,8 @@
 void	athn_btcoex_init(struct athn_softc *);
 int	athn_hw_reset(struct athn_softc *, struct ieee80211_channel *,
 	    struct ieee80211_channel *, int);
-void	athn_init_pll(struct athn_softc *, const struct ieee80211_channel *);
 void	athn_led_init(struct athn_softc *);
+void	athn_init_pll(struct athn_softc *, const struct ieee80211_channel *);
 int	athn_reset(struct athn_softc *, int);
 void	athn_reset_key(struct athn_softc *, int);
 void	athn_rx_start(struct athn_softc *);