Index: identcpu.c =================================================================== RCS file: /cvsroot/src/sys/arch/x86/x86/identcpu.c,v retrieving revision 1.33 diff -u -p -u -r1.33 identcpu.c --- identcpu.c 26 Jun 2013 20:52:28 -0000 1.33 +++ identcpu.c 26 Jun 2013 22:19:26 -0000 @@ -58,6 +58,7 @@ static const struct x86_cache_info amd_c AMD_L3CACHE_INFO; int cpu_vendor; +int cpu_msr_tsc; char cpu_brand_string[49]; /* @@ -563,14 +564,17 @@ cpu_probe_geode(struct cpu_info *ci) } static void -cpu_probe_qemu(struct cpu_info *ci) +cpu_probe_msr_tsc(struct cpu_info *ci) { - if (memcmp("QEMU Virtual CPU", cpu_brand_string, 16) != 0) - return; + cpu_msr_tsc = (cpu_feature[0] & CPUID_MSR) != 0; + if (!cpu_msr_tsc) + return; + + if (rdmsr(MSR_TSC) != 0) + return; - /* if QEMU does not implement MSR_TSC, disable the TSC */ - ci->ci_feat_val[0] &= ~CPUID_MSR; - cpu_feature[0] &= ~CPUID_MSR; + aprint_error_dev(ci->ci_dev, "Bad MSR_TSC support"); + cpu_msr_tsc = 0; } static void @@ -720,7 +724,7 @@ cpu_probe(struct cpu_info *ci) cpu_probe_c3(ci); cpu_probe_geode(ci); cpu_probe_vortex86(ci); - cpu_probe_qemu(ci); + cpu_probe_msr_tsc(ci); x86_cpu_topology(ci); Index: tsc.c =================================================================== RCS file: /cvsroot/src/sys/arch/x86/x86/tsc.c,v retrieving revision 1.30 diff -u -p -u -r1.30 tsc.c --- tsc.c 8 Aug 2011 17:00:23 -0000 1.30 +++ tsc.c 26 Jun 2013 22:19:26 -0000 @@ -258,10 +258,12 @@ cpu_hascounter(void) return cpu_feature[0] & CPUID_TSC; } +extern int cpu_msr_tsc; + uint64_t cpu_counter_serializing(void) { - if (cpu_feature[0] & CPUID_MSR) + if (cpu_msr_tsc) return rdmsr(MSR_TSC); else return cpu_counter();