From 12e7a107679f848ceb6b3ce6197720e637467617 Mon Sep 17 00:00:00 2001 From: Taylor R Campbell Date: Mon, 20 Jan 2020 05:53:36 +0000 Subject: [PATCH] WIP: Rockchip crypto engine RNG driver. There seem to be two versions of the Rockchip crypto engine, v1 and v2; this one is for v1. Can't name a driver `rkcryptov1' so we'll clumsily call it `rk1crypto' instead to leave room for `rk2crypto' later on. --- sys/arch/arm/dts/rk3399-pinebook-pro.dts | 10 + sys/arch/arm/dts/rk3399-rockpro64.dts | 9 + sys/arch/arm/rockchip/files.rockchip | 5 + sys/arch/arm/rockchip/rk_1crypto.c | 317 +++++++++++++++++++++++ sys/arch/arm/rockchip/rk_1crypto.h | 178 +++++++++++++ sys/arch/evbarm/conf/GENERIC64 | 1 + 6 files changed, 520 insertions(+) create mode 100644 sys/arch/arm/rockchip/rk_1crypto.c create mode 100644 sys/arch/arm/rockchip/rk_1crypto.h diff --git a/sys/arch/arm/dts/rk3399-pinebook-pro.dts b/sys/arch/arm/dts/rk3399-pinebook-pro.dts index 62c7d3f4640c..53546c013e6e 100644 --- a/sys/arch/arm/dts/rk3399-pinebook-pro.dts +++ b/sys/arch/arm/dts/rk3399-pinebook-pro.dts @@ -344,6 +344,16 @@ compatible = "universal-charger"; extcon = <&fusb0>; }; + + rng: rng@ff8b8000 { + compatible = "rockchip,cryptov1-rng"; + reg = <0x0 0xff8b8000 0x0 0x1000>; + clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>; + clock-names = "clk_crypto", "hclk_crypto"; + // ??? + // assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>; + // assigned-clock-rates = <150000000>, <100000000>; + }; }; &edp { diff --git a/sys/arch/arm/dts/rk3399-rockpro64.dts b/sys/arch/arm/dts/rk3399-rockpro64.dts index 0a42d0aaea38..ec6f53155bf5 100644 --- a/sys/arch/arm/dts/rk3399-rockpro64.dts +++ b/sys/arch/arm/dts/rk3399-rockpro64.dts @@ -148,6 +148,15 @@ }; #endif + rng: rng@ff8b8000 { + compatible = "rockchip,cryptov1-rng"; + reg = <0x0 0xff8b8000 0x0 0x1000>; + clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>; + clock-names = "clk_crypto", "hclk_crypto"; + // ??? + // assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>; + // assigned-clock-rates = <150000000>, <100000000>; + }; }; &pinctrl { diff --git a/sys/arch/arm/rockchip/files.rockchip b/sys/arch/arm/rockchip/files.rockchip index c11d8e9f47bf..d76eda96ca12 100644 --- a/sys/arch/arm/rockchip/files.rockchip +++ b/sys/arch/arm/rockchip/files.rockchip @@ -112,6 +112,11 @@ device rki2s attach rki2s at fdt with rk_i2s file arch/arm/rockchip/rk_i2s.c rk_i2s +# Crypto engine +device rk1crypto +attach rk1crypto at fdt with rk_1crypto +file arch/arm/rockchip/rk_1crypto.c rk_1crypto + # SOC parameters defflag opt_soc.h SOC_ROCKCHIP defflag opt_soc.h SOC_RK3328: SOC_ROCKCHIP diff --git a/sys/arch/arm/rockchip/rk_1crypto.c b/sys/arch/arm/rockchip/rk_1crypto.c new file mode 100644 index 000000000000..0b86d3d8ef80 --- /dev/null +++ b/sys/arch/arm/rockchip/rk_1crypto.c @@ -0,0 +1,317 @@ +/* $NetBSD$ */ + +/*- + * Copyright (c) 2020 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Taylor R. Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * rk_1crypto -- Rockchip crypto v1 driver + * + * This is just the RNG for now. + */ + +#include +__KERNEL_RCSID(1, "$NetBSD$"); + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +struct rk_1crypto_softc { + device_t sc_dev; + bus_space_tag_t sc_bst; + bus_space_handle_t sc_bsh; + kmutex_t sc_lock; + struct krndsource sc_rndsource; + struct rk_1crypto_sysctl { + struct sysctllog *cy_log; + const struct sysctlnode *cy_root_node; + const struct sysctlnode *cy_trng_node; + } sc_sysctl; +}; + +static int rk_1crypto_match(device_t, cfdata_t, void *); +static void rk_1crypto_attach(device_t, device_t, void *); +static void rk_1crypto_rndsource_attach(struct rk_1crypto_softc *); +static void rk_1crypto_rng_get(size_t, void *); +static void rk_1crypto_sysctl_attach(struct rk_1crypto_softc *); +static int rk_1crypto_sysctl_rng(SYSCTLFN_ARGS); +static int rk_1crypto_rng(struct rk_1crypto_softc *, + uint32_t[static RK_1CRYPTO_TRNG_NOUT]); + +static uint32_t +RKC_READ(struct rk_1crypto_softc *sc, bus_addr_t reg) +{ + return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); +} + +static void +RKC_WRITE(struct rk_1crypto_softc *sc, bus_addr_t reg, uint32_t v) +{ + return bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, v); +} + +static inline void +RKC_CTRL(struct rk_1crypto_softc *sc, uint16_t m, uint16_t v) +{ + uint32_t c = 0; + + c |= __SHIFTIN(m, RK_1CRYPTO_CTRL_MASK); + c |= __SHIFTIN(v, m); + RKC_WRITE(sc, RK_1CRYPTO_CTRL, c); +} + +CFATTACH_DECL_NEW(rk_1crypto, sizeof(struct rk_1crypto_softc), + rk_1crypto_match, rk_1crypto_attach, NULL, NULL); + +static const struct of_compat_data compat_data[] = { + /* XXX rockchip,rk3288-crypto? */ + {"rockchip,cryptov1-rng", 0}, + {NULL} +}; + +static int +rk_1crypto_match(device_t parent, cfdata_t cf, void *aux) +{ + const struct fdt_attach_args *const faa = aux; + + return of_match_compat_data(faa->faa_phandle, compat_data); +} + +static void +rk_1crypto_attach(device_t parent, device_t self, void *aux) +{ + struct rk_1crypto_softc *const sc = device_private(self); + const struct fdt_attach_args *const faa = aux; + bus_addr_t addr; + bus_size_t size; + const int phandle = faa->faa_phandle; + struct clk *clk; + + sc->sc_dev = self; + sc->sc_bst = faa->faa_bst; + mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); + + /* Get and map device registers. */ + if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { + aprint_error(": couldn't get registers\n"); + return; + } + if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { + aprint_error(": couldn't map registers\n"); + return; + } + + /* Enable the clocks. */ + if ((clk = fdtbus_clock_get(phandle, "clk_crypto")) != NULL) { + if (clk_enable(clk) != 0) { + aprint_error(": couldn't enable clk_crypto\n"); + return; + } + if (clk_set_rate(clk, 150*1000*1000) != 0) { + aprint_error(": couldn't set clk_crypto to 150MHz\n"); + return; + } + } + if ((clk = fdtbus_clock_get(phandle, "hclk_crypto")) != NULL) { + if (clk_enable(clk) != 0) { + aprint_error(": couldn't enable hclk_crypto\n"); + return; + } + if (clk_set_rate(clk, 100*1000*1000) != 0) { + aprint_error(": couldn't set hclk_crypto to 100MHz\n"); + return; + } + } + + aprint_naive("\n"); + aprint_normal(": Crypto v1\n"); + + rk_1crypto_rndsource_attach(sc); + rk_1crypto_sysctl_attach(sc); +} + +static void +rk_1crypto_rndsource_attach(struct rk_1crypto_softc *sc) +{ + device_t self = sc->sc_dev; + + rndsource_setcb(&sc->sc_rndsource, rk_1crypto_rng_get, sc); + rnd_attach_source(&sc->sc_rndsource, device_xname(self), + RND_TYPE_RNG, /* XXX */ + RND_FLAG_COLLECT_VALUE|RND_FLAG_ESTIMATE_VALUE|RND_FLAG_HASCB); +} + +static void +rk_1crypto_rng_get(size_t nbytes, void *cookie) +{ + struct rk_1crypto_softc *sc = cookie; + device_t self = sc->sc_dev; + uint32_t buf[RK_1CRYPTO_TRNG_NOUT]; + uint32_t entropybits = NBBY*sizeof(buf); + unsigned n = RK_1CRYPTO_TRNG_NOUT; + int error; + + CTASSERT((RK_1CRYPTO_TRNG_NOUT % 2) == 0); + + error = rk_1crypto_rng(sc, buf); + if (error) + entropybits = 0; + if (consttime_memequal(buf, buf + n/2, n/2)) { + device_printf(self, "failed repeated output test\n"); + entropybits = 0; + } + + rnd_add_data(&sc->sc_rndsource, buf, sizeof buf, entropybits); + explicit_memset(buf, 0, sizeof buf); +} + +static void +rk_1crypto_sysctl_attach(struct rk_1crypto_softc *sc) +{ + device_t self = sc->sc_dev; + struct rk_1crypto_sysctl *cy = &sc->sc_sysctl; + int error; + + /* hw.rk1cryptoN (node) */ + error = sysctl_createv(&cy->cy_log, 0, NULL, &cy->cy_root_node, + CTLFLAG_PERMANENT, CTLTYPE_NODE, device_xname(self), + SYSCTL_DESCR("rk crypto v1 engine knobs"), + NULL, 0, NULL, 0, + CTL_HW, CTL_CREATE, CTL_EOL); + if (error) { + aprint_error_dev(self, + "failed to set up sysctl hw.%s: %d\n", + device_xname(self), error); + return; + } + + /* hw.rk1cryptoN.rng (`struct', 32-byte array) */ + sysctl_createv(&cy->cy_log, 0, &cy->cy_trng_node, NULL, + CTLFLAG_PERMANENT|CTLFLAG_READONLY|CTLFLAG_PRIVATE, CTLTYPE_STRUCT, + "rng", SYSCTL_DESCR("Read up to 32 bytes out of the TRNG"), + &rk_1crypto_sysctl_rng, 0, sc, 0, CTL_CREATE, CTL_EOL); + if (error) { + aprint_error_dev(self, + "failed to set up sysctl hw.%s.rng: %d\n", + device_xname(self), error); + return; + } +} + +static int +rk_1crypto_sysctl_rng(SYSCTLFN_ARGS) +{ + uint32_t buf[RK_1CRYPTO_TRNG_NOUT]; + struct sysctlnode node = *rnode; + struct rk_1crypto_softc *sc = node.sysctl_data; + size_t size; + int error; + + /* If oldp == NULL, the caller wants to learn the size. */ + if (oldp == NULL) { + *oldlenp = sizeof buf; + return 0; + } + + /* Verify the output buffer size is reasonable. */ + size = *oldlenp; + if (size > sizeof buf) /* size_t, so never negative */ + return E2BIG; + if (size == 0) + return 0; /* nothing to do */ + + /* Generate data. */ + error = rk_1crypto_rng(sc, buf); + if (error) + return error; + + /* Copy out the data. */ + node.sysctl_data = buf; + node.sysctl_size = size; + error = sysctl_lookup(SYSCTLFN_CALL(&node)); + + /* Clear the buffer. */ + explicit_memset(buf, 0, sizeof buf); + + /* Return the sysctl_lookup error, if any. */ + return error; +} + +static int +rk_1crypto_rng(struct rk_1crypto_softc *sc, + uint32_t buf[static RK_1CRYPTO_TRNG_NOUT]) +{ + uint32_t ctrl; + unsigned i, timo; + int error; + + /* Acquire lock to serialize access to TRNG. */ + mutex_enter(&sc->sc_lock); + + /* + * Enable ring oscillator to start gathering entropy for a + * sample period of 100 cycles. (XXX Why 100?) + */ + ctrl = RK_1CRYPTO_TRNG_CTRL_OSC_ENABLE; + ctrl |= __SHIFTIN(100, RK_1CRYPTO_TRNG_CTRL_CYCLES); + RKC_WRITE(sc, RK_1CRYPTO_TRNG_CTRL, ctrl); + + /* Enable TRNG and wait up to 10ms = 100*100us for it to post. */ + RKC_CTRL(sc, RK_1CRYPTO_CTRL_TRNG_START, 1); + timo = 100; + while ((RKC_READ(sc, RK_1CRYPTO_CTRL) & RK_1CRYPTO_CTRL_TRNG_START) + == 0) { + if (--timo == 0) { + error = ETIMEDOUT; + goto out; + } + DELAY(100); + } + + /* Read out the data. */ + for (i = 0; i < 8; i++) + buf[i] = RKC_READ(sc, RK_1CRYPTO_TRNG_DOUT(i)); + + /* Success! */ + error = 0; + +out: /* Disable TRNG and release lock. */ + RKC_CTRL(sc, RK_1CRYPTO_CTRL_TRNG_START, 0); + mutex_exit(&sc->sc_lock); + return error; +} diff --git a/sys/arch/arm/rockchip/rk_1crypto.h b/sys/arch/arm/rockchip/rk_1crypto.h new file mode 100644 index 000000000000..c01a5d29d38e --- /dev/null +++ b/sys/arch/arm/rockchip/rk_1crypto.h @@ -0,0 +1,178 @@ +/* $NetBSD$ */ + +/*- + * Copyright (c) 2020 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Taylor R. Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM_ROCKCHIP_RK_1CRYPTO_H +#define _ARM_ROCKCHIP_RK_1CRYPTO_H + +#define RK_1CRYPTO_INTSTS 0x0000 /* Interrupt Status */ +#define RK_1CRYPTO_INTSTS_PKA_DONE __BIT(5) +#define RK_1CRYPTO_INTSTS_HASH_DONE __BIT(4) +#define RK_1CRYPTO_INTSTS_HRDMA_ERR __BIT(3) +#define RK_1CRYPTO_INTSTS_HRDMA_DONE __BIT(2) +#define RK_1CRYPTO_INTSTS_BCDMA_ERR __BIT(1) +#define RK_1CRYPTO_INTSTS_BCDMA_DONE __BIT(0) + +#define RK_1CRYPTO_INTENA 0x0004 /* Interrupt Enable */ +#define RK_1CRYPTO_INTENA_PKA_DONE __BIT(5) +#define RK_1CRYPTO_INTENA_HASH_DONE __BIT(4) +#define RK_1CRYPTO_INTENA_HRDMA_ERR __BIT(3) +#define RK_1CRYPTO_INTENA_HRDMA_DONE __BIT(2) +#define RK_1CRYPTO_INTENA_BCDMA_ERR __BIT(1) +#define RK_1CRYPTO_INTENA_BCDMA_DONE __BIT(0) + +#define RK_1CRYPTO_CTRL 0x0008 /* Control */ +#define RK_1CRYPTO_CTRL_MASK __BITS(31,16) +#define RK_1CRYPTO_CTRL_TRNG_FLUSH __BIT(9) +#define RK_1CRYPTO_CTRL_TRNG_START __BIT(8) +#define RK_1CRYPTO_CTRL_PKA_FLUSH __BIT(7) +#define RK_1CRYPTO_CTRL_HASH_FLUSH __BIT(6) +#define RK_1CRYPTO_CTRL_BLOCK_FLUSH __BIT(5) +#define RK_1CRYPTO_CTRL_PKA_START __BIT(4) +#define RK_1CRYPTO_CTRL_HASH_START __BIT(3) +#define RK_1CRYPTO_CTRL_BLOCK_START __BIT(2) +#define RK_1CRYPTO_CTRL_TDES_START __BIT(1) +#define RK_1CRYPTO_CTRL_AES_START __BIT(0) + +#define RK_1CRYPTO_CONF 0x000c /* ? */ +#define RK_1CRYPTO_CONF_HR_ADDR_MODE __BIT(8) +#define RK_1CRYPTO_CONF_BT_ADDR_MODE __BIT(7) +#define RK_1CRYPTO_CONF_BR_ADDR_MODE __BIT(6) +#define RK_1CRYPTO_CONF_MODE_FIX 1 +#define RK_1CRYPTO_CONF_MODE_INCR 0 +#define RK_1CRYPTO_CONF_BYTESWAP_HRFIFO __BIT(5) +#define RK_1CRYPTO_CONF_BYTESWAP_BTFIFO __BIT(4) +#define RK_1CRYPTO_CONF_BYTESWAP_BRFIFO __BIT(3) +#define RK_1CRYPTO_CONF_DESSEL __BIT(2) +#define RK_1CRYPTO_CONF_DESSEL_AES 0 +#define RK_1CRYPTO_CONF_DESSEL_DES 1 /* 3DES? */ +#define RK_1CRYPTO_CONF_HASHINSEL __BITS(1,0) +#define RK_1CRYPTO_CONF_HASHINSEL_INDEP 0 +#define RK_1CRYPTO_CONF_HASHINSEL_BLKIN 1 +#define RK_1CRYPTO_CONF_HASHINSEL_BLKOUT 2 + +#define RK_1CRYPTO_BRDMAS 0x0010 /* Block Rx DMA Start */ +#define RK_1CRYPTO_BTDMAS 0x0014 /* Block Tx DMA Start */ +#define RK_1CRYPTO_BRDMAL 0x0018 /* Block Rx DMA Length */ +#define RK_1CRYPTO_BTDMAL 0x0020 /* Block Tx DMA Length */ +#define RK_1CRYPTO_HRDMAS 0x001c /* Hash Rx DMA Start */ +#define RK_1CRYPTO_HRDMAL 0x0020 /* Hash Rx DMA Length */ + +#define RK_1CRYPTO_AES_CTRL 0x0080 /* AES Control */ +#define RK_1CRYPTO_AES_CTRL_BYTESWAP_CNT __BIT(11) +#define RK_1CRYPTO_AES_CTRL_BYTESWAP_KEY __BIT(10) +#define RK_1CRYPTO_AES_CTRL_BYTESWAP_IV __BIT(9) +#define RK_1CRYPTO_AES_CTRL_BYTESWAP_DO __BIT(8) +#define RK_1CRYPTO_AES_CTRL_BYTESWAP_DI __BIT(7) +#define RK_1CRYPTO_AES_CTRL_KEYCHANGE __BIT(6) +#define RK_1CRYPTO_AES_CTRL_MODE __BITS(5,4) +#define RK_1CRYPTO_AES_CTRL_MODE_ECB 0 +#define RK_1CRYPTO_AES_CTRL_MODE_CBC 1 +#define RK_1CRYPTO_AES_CTRL_MODE_CTR 2 +#define RK_1CRYPTO_AES_CTRL_KEYSIZE __BITS(3,2) +#define RK_1CRYPTO_AES_CTRL_KEYSIZE_128 0 +#define RK_1CRYPTO_AES_CTRL_KEYSIZE_192 1 +#define RK_1CRYPTO_AES_CTRL_KEYSIZE_256 2 +#define RK_1CRYPTO_AES_CTRL_FIFOMODE __BIT(1) +#define RK_1CRYPTO_AES_CTRL_DIR __BIT(0) +#define RK_1CRYPTO_AES_CTRL_DIR_ENC 0 +#define RK_1CRYPTO_AES_CTRL_DIR_DEC 1 + +#define RK_1CRYPTO_AES_STS 0x0084 /* AES Status */ +#define RK_1CRYPTO_AES_STS_DONE __BIT(0) + +#define RK_1CRYPTO_AES_DIN(n) (0x0088 + 4*(n)) /* AES Input */ +#define RK_1CRYPTO_AES_DOUT(n) (0x0098 + 4*(n)) /* AES Output */ +#define RK_1CRYPTO_AES_IV(n) (0x00a8 + 4*(n)) /* AES IV */ +#define RK_1CRYPTO_AES_KEY(n) (0x00b8 + 4*(n)) /* AES Key */ +#define RK_1CRYPTO_AES_CNT(n) (0x00d8 + 4*(n)) /* AES Input Counter */ + +#define RK_1CRYPTO_TDES_CTRL 0x0100 /* 3DES Control */ +#define RK_1CRYPTO_TDES_CTRL_BYTESWAP_KEY __BIT(8) +#define RK_1CRYPTO_TDES_CTRL_BYTESWAP_IV __BIT(7) +#define RK_1CRYPTO_TDES_CTRL_BYTESWAP_DO __BIT(6) +#define RK_1CRYPTO_TDES_CTRL_BYTESWAP_DI __BIT(5) +#define RK_1CRYPTO_TDES_CTRL_MODE __BIT(4) +#define RK_1CRYPTO_TDES_CTRL_MODE_ECB 0 +#define RK_1CRYPTO_TDES_CTRL_MODE_CBC 1 +#define RK_1CRYPTO_TDES_CTRL_KEYMODE __BIT(3) +#define RK_1CRYPTO_TDES_CTRL_KEYMODE_EDE 0 +#define RK_1CRYPTO_TDES_CTRL_KEYMODE_EEE 1 +#define RK_1CRYPTO_TDES_CTRL_SELECT __BIT(2) +#define RK_1CRYPTO_TDES_CTRL_SELECT_DES 0 +#define RK_1CRYPTO_TDES_CTRL_SELECT_TDES 1 +#define RK_1CRYPTO_TDES_CTRL_FIFOMODE __BIT(1) +#define RK_1CRYPTO_TDES_CTRL_DIR __BIT(0) +#define RK_1CRYPTO_TDES_CTRL_DIR_ENC 0 +#define RK_1CRYPTO_TDES_CTRL_DIR_DEC 1 + +#define RK_1CRYPTO_TDES_STS 0x0104 /* 3DES Status */ +#define RK_1CRYPTO_TDES_STS_DONE __BIT(0) + +#define RK_1CRYPTO_TDES_DIN(n) (0x0108 + 4*(n)) /* 3DES Input */ +#define RK_1CRYPTO_TDES_DOUT(n)(0x0110 + 4*(n)) /* 3DES Output */ +#define RK_1CRYPTO_TDES_IV(n) (0x0118 + 4*(n)) /* 3DES IV */ +#define RK_1CRYPTO_TDES_KEY(n) (0x0120 + 4*(n)) /* 3DES Key(1,2,3) */ + +#define RK_1CRYPTO_HASH_CTRL 0x0180 /* Hash Control */ +#define RK_1CRYPTO_HASH_SWAP_DO __BIT(3) +#define RK_1CRYPTO_HASH_SWAP_DI __BIT(2) +#define RK_1CRYPTO_HASH_SELECT __BITS(1,0) +#define RK_1CRYPTO_HASH_SELECT_SHA1 0 +#define RK_1CRYPTO_HASH_SELECT_MD5 1 +#define RK_1CRYPTO_HASH_SELECT_SHA256 2 +#define RK_1CRYPTO_HASH_SELECT_PRNG 3 /* ??? */ + +#define RK_1CRYPTO_HASH_STS 0x0184 /* Hash Status */ +#define RK_1CRYPTO_HASH_STS_DONE __BIT(0) + +#define RK_1CRYPTO_HASH_MSG_LEN 0x0188 /* Hash Message Len */ +#define RK_1CRYPTO_HASH_DOUT(n)(0x018c + 4*(n)) /* Hash Result */ +#define RK_1CRYPTO_HASH_SEED(n)(0x01ac + 4*(n)) /* HMAC/PRNG key */ + +#define RK_1CRYPTO_TRNG_CTRL 0x0200 /* TRNG Control */ +#define RK_1CRYPTO_TRNG_CTRL_OSC_ENABLE __BIT(16) +#define RK_1CRYPTO_TRNG_CTRL_CYCLES __BITS(15,0) + +#define RK_1CRYPTO_TRNG_DOUT(n)(0x0204 + 4*(n)) /* TRNG Output */ +#define RK_1CRYPTO_TRNG_NOUT 8 /* up to 8 32-bit */ + +#define RK_1CRYPTO_PKA_CTRL 0x0280 /* PKA Control (RSA?) */ +#define RK_1CRYPTO_PKA_CTRL_SIZE __BITS(1,0) +#define RK_1CRYPTO_PKA_CTRL_SIZE_512 0 +#define RK_1CRYPTO_PKA_CTRL_SIZE_1024 1 +#define RK_1CRYPTO_PKA_CTRL_SIZE_2048 2 + +#define RK_1CRYPTO_M 0x0400 /* RSA `message' */ +#define RK_1CRYPTO_C 0x0500 /* 2^(2 ceil(lg n) + 2) mod n */ +#define RK_1CRYPTO_N 0x0600 /* RSA modulus? */ +#define RK_1CRYPTO_E 0x0700 /* RSA exponent? */ + +#endif /* _ARM_ROCKCHIP_RK_1CRYPTO_H */ diff --git a/sys/arch/evbarm/conf/GENERIC64 b/sys/arch/evbarm/conf/GENERIC64 index 773abc723906..b9a4200b7465 100644 --- a/sys/arch/evbarm/conf/GENERIC64 +++ b/sys/arch/evbarm/conf/GENERIC64 @@ -411,6 +411,7 @@ amdccp* at acpi? bcmrng* at fdt? # Broadcom BCM283x RNG mesonrng* at fdt? # Amlogic Meson RNG sun8icrypto* at fdt? # Allwinner Crypto Engine +rk1crypto* at fdt? # Rockchip Crypto v1 # RTC plrtc* at fdt? # ARM PrimeCell RTC