Index: sun50i_a64_ccu.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/sunxi/sun50i_a64_ccu.c,v
retrieving revision 1.13
diff -u -p -r1.13 sun50i_a64_ccu.c
--- sun50i_a64_ccu.c	1 Jul 2019 21:06:47 -0000	1.13
+++ sun50i_a64_ccu.c	5 Jul 2019 14:47:26 -0000
@@ -64,6 +64,7 @@ __KERNEL_RCSID(1, "$NetBSD: sun50i_a64_c
 #define	DRAM_CFG_REG		0x0f4
 #define	MBUS_RST_REG		0x0fc
 #define	DE_CLK_REG		0x104
+#define	TCON0_CLK_REG		0x118
 #define	TCON1_CLK_REG		0x11c
 #define	AC_DIG_CLK_REG		0x140
 #define	HDMI_CLK_REG		0x150
@@ -154,6 +155,7 @@ static const char *mmc_parents[] = { "ho
 static const char *ths_parents[] = { "hosc", NULL, NULL, NULL };
 static const char *de_parents[] = { "pll_periph0_2x", "pll_de" };
 static const char *hdmi_parents[] = { "pll_video0", "pll_video1" };
+static const char *tcon0_parents[] = { "pll_mipi", NULL, "pll_video0_2x", NULL };
 static const char *tcon1_parents[] = { "pll_video0", NULL, "pll_video1", NULL };
 static const char *gpu_parents[] = { "pll_gpu" };
 
@@ -407,6 +409,13 @@ static struct sunxi_ccu_clk sun50i_a64_c
 	SUNXI_CCU_GATE(A64_CLK_HDMI_DDC, "hdmi-ddc", "hosc",
 	    HDMI_SLOW_CLK_REG, 31),
 
+	SUNXI_CCU_DIV_GATE(A64_CLK_TCON0, "tcon0", tcon0_parents,
+	    TCON0_CLK_REG,	/* reg */
+	    0,			/* div */
+	    __BITS(26,24),	/* sel */
+	    __BIT(31),		/* enable */
+	    SUNXI_CCU_DIV_SET_RATE_PARENT),
+
 	SUNXI_CCU_DIV_GATE(A64_CLK_TCON1, "tcon1", tcon1_parents,
 	    TCON1_CLK_REG,	/* reg */
 	    __BITS(3,0),	/* div */
Index: sunxi_lcdc.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/sunxi/sunxi_lcdc.c,v
retrieving revision 1.5
diff -u -p -r1.5 sunxi_lcdc.c
--- sunxi_lcdc.c	18 Feb 2019 02:42:27 -0000	1.5
+++ sunxi_lcdc.c	5 Jul 2019 14:47:26 -0000
@@ -212,7 +212,13 @@ sunxi_lcdc_tcon0_commit(struct drm_encod
 	struct sunxi_lcdc_softc * const sc = lcdc_encoder->sc;
 	struct drm_display_mode *mode = &lcdc_encoder->curmode;
 	uint32_t val;
-	int error;
+	/*
+	 * XXX: was: uint32_t val, div;
+	 * XXX: ...but div is unused (it is assigned but never used)
+	 */
+	/*
+	 * XXX: not used: int error;
+	 */
 
 	const u_int interlace_p = (mode->flags & DRM_MODE_FLAG_INTERLACE) != 0;
 	const u_int hspw = mode->hsync_end - mode->hsync_start;
@@ -228,6 +234,17 @@ sunxi_lcdc_tcon0_commit(struct drm_encod
 	      __SHIFTIN(start_delay, TCON0_CTL_START_DELAY);
 	TCON_WRITE(sc, TCON0_CTL_REG, val);
 
+	if (sc->sc_clk_ch[0] != NULL) {
+		/* XXX: should them be used?
+		parent_rate = clk_get_rate(sc->sc_clk_ch[0]);
+		div = parent_rate / (mode->crtc_clock * 1000);
+		*/
+		val = TCON0_DCLK_EN | __SHIFTIN(val, TCON0_DCLK_DIV);
+		TCON_WRITE(sc, TCON0_DCLK_REG, val);
+	} else {
+		device_printf(sc->sc_dev, "no CH0 PLL configured\n");
+	}
+
 	TCON_WRITE(sc, TCON0_BASIC0_REG, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
 	TCON_WRITE(sc, TCON0_BASIC1_REG, ((mode->htotal - 1) << 16) | (hbp - 1));
 	TCON_WRITE(sc, TCON0_BASIC2_REG, ((mode->vtotal * 2) << 16) | (vbp - 1));
@@ -242,22 +259,6 @@ sunxi_lcdc_tcon0_commit(struct drm_encod
 	if ((mode->flags & DRM_MODE_FLAG_PVSYNC) == 0)
 		val |= TCON0_IO_POL_IO0_INV;
 	TCON_WRITE(sc, TCON0_IO_POL_REG, val);
-
-	if (sc->sc_clk_ch[0] != NULL) {
-		error = clk_set_rate(sc->sc_clk_ch[0], mode->crtc_clock * 1000);
-		if (error != 0) {
-			device_printf(sc->sc_dev, "failed to set CH0 PLL rate to %u Hz: %d\n",
-			    mode->crtc_clock * 1000, error);
-			return;
-		}
-		error = clk_enable(sc->sc_clk_ch[0]);
-		if (error != 0) {
-			device_printf(sc->sc_dev, "failed to enable CH0 PLL: %d\n", error);
-			return;
-		}
-	} else {
-		device_printf(sc->sc_dev, "no CH0 PLL configured\n");
-	}
 }
 
 static void