Index: sys/arch/arm/arm/arm_machdep.c
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/arm/arm_machdep.c,v
retrieving revision 1.64
diff -p -u -r1.64 arm_machdep.c
--- sys/arch/arm/arm/arm_machdep.c	14 Aug 2020 16:18:36 -0000	1.64
+++ sys/arch/arm/arm/arm_machdep.c	24 Nov 2020 07:33:39 -0000
@@ -176,15 +176,14 @@ setregs(struct lwp *l, struct exec_packa
 	tf->tf_usr_lr = pack->ep_entry;
 	tf->tf_svc_lr = 0x77777777;		/* Something we can see */
 	tf->tf_pc = pack->ep_entry;
-#if defined(__ARMEB__)
+	tf->tf_spsr = PSR_USR32_MODE;
+#ifdef _ARM_ARCH_BE8
 	/*
-	 * If we are running on ARMv7, we need to set the E bit to force
-	 * programs to start as big endian.
+	 * If we are running on BE8 mode, we need to set the E bit to
+	 * force programs to start as big endian.
 	 */
-	tf->tf_spsr = PSR_USR32_MODE | (CPU_IS_ARMV7_P() ? PSR_E_BIT : 0);
-#else
-	tf->tf_spsr = PSR_USR32_MODE;
-#endif /* __ARMEB__ */
+	tf->tf_spsr |= PSR_E_BIT;
+#endif
 
 #ifdef THUMB_CODE
 	if (pack->ep_entry & 1)
Index: sys/arch/arm/arm/armv6_start.S
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/arm/armv6_start.S,v
retrieving revision 1.30
diff -p -u -r1.30 armv6_start.S
--- sys/arch/arm/arm/armv6_start.S	13 Oct 2020 21:06:18 -0000	1.30
+++ sys/arch/arm/arm/armv6_start.S	24 Nov 2020 03:19:46 -0000
@@ -95,9 +95,16 @@
 
 ENTRY_NP(generic_start)
 
-	// ARMv7 only?!?
 #if defined(__ARMEB__)
+#  if defined(_ARM_ARCH_7)
 	setend	be			/* force big endian */
+#  else
+	/* Make sure U bit is always set with E bit in CP15 Reg 1. */
+	mrc	p15, 0, R_TMP1, c1, c0, 0
+	orr	R_TMP1, R_TMP1, #CPU_CONTROL_UNAL_ENABLE
+	mcr     p15, 0, R_TMP1, c1, c0, 0
+	setend	be
+#  endif
 #endif
 
 	/* disable IRQs/FIQs. */
@@ -1086,6 +1093,11 @@ Lcontrol_set:
 #else
 #define	CPU_CONTROL_EXTRA	CPU_CONTROL_SYST_ENABLE
 #endif
+#if defined(__ARMEL__)
+#define	CPU_CONTROL_EX_BEND_SET	0
+#else
+#define	CPU_CONTROL_EX_BEND_SET	CPU_CONTROL_EX_BEND
+#endif
 	.word CPU_CONTROL_MMU_ENABLE  | \
 	      CPU_CONTROL_WBUF_ENABLE |    /* not defined in 1176 (SBO) */ \
 	      CPU_CONTROL_32BP_ENABLE |    /* SBO */ \
@@ -1094,7 +1106,8 @@ Lcontrol_set:
 		(1 << 16) | 	/* SBO - Global enable for data tcm */ \
 		(1 << 18) |	/* SBO - Global enable for insn tcm */ \
 	      CPU_CONTROL_UNAL_ENABLE | \
-	      CPU_CONTROL_EXTRA
+	      CPU_CONTROL_EXTRA | \
+	      CPU_CONTROL_EX_BEND_SET
 
 	/* bits to clear in the Control Register */
 Lcontrol_clr:
Index: sys/arch/arm/arm/cpu_exec.c
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/arm/cpu_exec.c,v
retrieving revision 1.12
diff -p -u -r1.12 cpu_exec.c
--- sys/arch/arm/arm/cpu_exec.c	12 Nov 2020 01:03:22 -0000	1.12
+++ sys/arch/arm/arm/cpu_exec.c	24 Nov 2020 07:34:23 -0000
@@ -111,7 +111,14 @@ arm_netbsd_elf32_probe(struct lwp *l, st
 	 * If we are AAPCS (EABI) and armv6/armv7, we want alignment faults
 	 * to be off.
 	 */
-	if (aapcs_p && (CPU_IS_ARMV7_P() || CPU_IS_ARMV6_P())) {
+#if defined(__ARMEL__)
+	if (aapcs_p && (CPU_IS_ARMV7_P() || CPU_IS_ARMV6_P()))
+#elif defined(_ARM_ARCH_BE8)
+	if (aapcs_p)
+#else
+	if (false /* CONSTCOND */)
+#endif
+	{
 		l->l_md.md_flags |= MDLWP_NOALIGNFLT;
 	} else {
 		l->l_md.md_flags &= ~MDLWP_NOALIGNFLT;
Index: sys/arch/arm/arm/cpufunc.c
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/arm/cpufunc.c,v
retrieving revision 1.178
diff -p -u -r1.178 cpufunc.c
--- sys/arch/arm/arm/cpufunc.c	30 Oct 2020 18:54:36 -0000	1.178
+++ sys/arch/arm/arm/cpufunc.c	24 Nov 2020 02:45:16 -0000
@@ -2769,6 +2769,11 @@ arm11_setup(char *args)
 #endif
 	    | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
 	    /* | CPU_CONTROL_BPRD_ENABLE */;
+
+#ifdef __ARMEB__
+	cpuctrl |= CPU_CONTROL_EX_BEND;
+#endif
+
 	int cpuctrlmask = cpuctrl
 	    | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BPRD_ENABLE
 	    | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
@@ -2780,10 +2785,6 @@ arm11_setup(char *args)
 
 	cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl);
 
-#ifdef __ARMEB__
-	cpuctrl |= CPU_CONTROL_BEND_ENABLE;
-#endif
-
 #ifndef ARM_HAS_VBAR
 	if (vector_page == ARM_VECTORS_HIGH)
 		cpuctrl |= CPU_CONTROL_VECRELOC;
@@ -2818,6 +2819,11 @@ arm11mpcore_setup(char *args)
 	    | CPU_CONTROL_XP_ENABLE
 #endif
 	    | CPU_CONTROL_BPRD_ENABLE ;
+
+#ifdef __ARMEB__
+	cpuctrl |= CPU_CONTROL_EX_BEND;
+#endif
+
 	int cpuctrlmask = cpuctrl
 	    | CPU_CONTROL_AFLT_ENABLE
 	    | CPU_CONTROL_VECRELOC;
@@ -3057,6 +3063,10 @@ arm11x6_setup(char *args)
 #endif
 		CPU_CONTROL_IC_ENABLE;
 
+#ifdef __ARMEB__
+	cpuctrl |= CPU_CONTROL_EX_BEND;
+#endif
+
 	/*
 	 * "write as existing" bits
 	 * inverse of this is mask
@@ -3075,10 +3085,6 @@ arm11x6_setup(char *args)
 
 	cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl);
 
-#ifdef __ARMEB__
-	cpuctrl |= CPU_CONTROL_BEND_ENABLE;
-#endif
-
 #ifndef ARM_HAS_VBAR
 	if (vector_page == ARM_VECTORS_HIGH)
 		cpuctrl |= CPU_CONTROL_VECRELOC;
Index: sys/arch/arm/arm/disassem.c
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/arm/disassem.c,v
retrieving revision 1.41
diff -p -u -r1.41 disassem.c
--- sys/arch/arm/arm/disassem.c	24 Oct 2019 18:34:22 -0000	1.41
+++ sys/arch/arm/arm/disassem.c	24 Nov 2020 07:34:48 -0000
@@ -447,7 +447,7 @@ disasm(const disasm_interface_t *di, vad
 	fmt = 0;
 	matchp = 0;
 	insn = di->di_readword(loc);
-#if defined(__ARMEB__) && defined(CPU_ARMV7)
+#ifdef _ARM_ARCH_BE8
 	insn = bswap32(insn);
 #endif
 	char neonfmt = 'd';
Index: sys/arch/arm/arm32/arm32_boot.c
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/arm32/arm32_boot.c,v
retrieving revision 1.40
diff -p -u -r1.40 arm32_boot.c
--- sys/arch/arm/arm32/arm32_boot.c	11 Sep 2020 06:40:25 -0000	1.40
+++ sys/arch/arm/arm32/arm32_boot.c	24 Nov 2020 07:35:11 -0000
@@ -191,10 +191,9 @@ initarm_common(vaddr_t kvm_base, vsize_t
 	memset(tf, 0, sizeof(*tf));
 	lwp_settrapframe(l, tf);
 
-#if defined(__ARMEB__)
-	tf->tf_spsr = PSR_USR32_MODE | (CPU_IS_ARMV7_P() ? PSR_E_BIT : 0);
-#else
  	tf->tf_spsr = PSR_USR32_MODE;
+#ifdef _ARM_ARCH_BE8
+	tf->tf_spsr |= PSR_E_BIT;
 #endif
 
 	VPRINTF("bootstrap done.\n");
Index: sys/arch/arm/arm32/arm32_machdep.c
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/arm32/arm32_machdep.c,v
retrieving revision 1.138
diff -p -u -r1.138 arm32_machdep.c
--- sys/arch/arm/arm32/arm32_machdep.c	30 Oct 2020 18:54:36 -0000	1.138
+++ sys/arch/arm/arm32/arm32_machdep.c	24 Nov 2020 07:35:38 -0000
@@ -348,10 +348,9 @@ cpu_startup(void)
 	memset(tf, 0, sizeof(*tf));
 	lwp_settrapframe(l, tf);
 
-#if defined(__ARMEB__)
-	tf->tf_spsr = PSR_USR32_MODE | (CPU_IS_ARMV7_P() ? PSR_E_BIT : 0);
-#else
  	tf->tf_spsr = PSR_USR32_MODE;
+#ifdef _ARM_ARCH_BE8
+	tf->tf_spsr |= PSR_E_BIT;
 #endif
 
 	cpu_startup_hook();
@@ -538,7 +537,14 @@ SYSCTL_SETUP(sysctl_machdep_setup, "sysc
 		       CTLTYPE_INT, "printfataltraps", NULL,
 		       NULL, 0, &cpu_printfataltraps, 0,
 		       CTL_MACHDEP, CTL_CREATE, CTL_EOL);
-	cpu_unaligned_sigbus = !CPU_IS_ARMV6_P() && !CPU_IS_ARMV7_P();
+	cpu_unaligned_sigbus =
+#if defined(__ARMEL__)
+	    !CPU_IS_ARMV6_P() && !CPU_IS_ARMV7_P();
+#elif defined(_ARM_ARCH_BE8)
+	    0;
+#else
+	    1;
+#endif
 	sysctl_createv(clog, 0, NULL, NULL,
 		       CTLFLAG_PERMANENT|CTLFLAG_READONLY,
 		       CTLTYPE_INT, "unaligned_sigbus",
Index: sys/arch/arm/arm32/db_interface.c
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/arm32/db_interface.c,v
retrieving revision 1.61
diff -p -u -r1.61 db_interface.c
--- sys/arch/arm/arm32/db_interface.c	20 Jun 2020 15:45:22 -0000	1.61
+++ sys/arch/arm/arm32/db_interface.c	24 Nov 2020 07:35:56 -0000
@@ -303,10 +303,10 @@ db_write_bytes(vaddr_t addr, size_t size
 void
 cpu_Debugger(void)
 {
-#if _BYTE_ORDER == _LITTLE_ENDIAN
-	__asm(".word	0xe7ffffff");
-#else
+#ifdef _ARM_ARCH_BE8
 	__asm(".word	0xffffffe7");
+#else
+	__asm(".word	0xe7ffffff");
 #endif
 }
 
Index: sys/arch/arm/arm32/kobj_machdep.c
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/arm32/kobj_machdep.c,v
retrieving revision 1.14
diff -p -u -r1.14 kobj_machdep.c
--- sys/arch/arm/arm32/kobj_machdep.c	20 Jun 2020 07:10:36 -0000	1.14
+++ sys/arch/arm/arm32/kobj_machdep.c	24 Nov 2020 07:36:20 -0000
@@ -400,8 +400,8 @@ kobj_machdep(kobj_t ko, void *base, size
 {
 
 	if (load) {
-#if __ARMEB__
-		if (CPU_IS_ARMV7_P() && base == (void*)ko->ko_text_address)
+#ifdef _ARM_ARCH_BE8
+		if (base == (void*)ko->ko_text_address)
 			kobj_be8_fixup(ko);
 #endif
 #ifndef _RUMPKERNEL
Index: sys/arch/arm/include/cdefs.h
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/include/cdefs.h,v
retrieving revision 1.18
diff -p -u -r1.18 cdefs.h
--- sys/arch/arm/include/cdefs.h	3 Nov 2020 08:34:17 -0000	1.18
+++ sys/arch/arm/include/cdefs.h	24 Nov 2020 07:33:14 -0000
@@ -55,6 +55,10 @@
 #define	_ARM_ARCH_DWORD_OK
 #endif
 
+#if defined (__ARMEB__) && defined (_ARM_ARCH_6)
+#define	_ARM_ARCH_BE8
+#endif
+
 #if defined(__ARM_PCS_AAPCS64)
 #define __ALIGNBYTES		(sizeof(__int128_t) - 1)
 #elif defined(__ARM_EABI__)
Index: sys/arch/arm/include/db_machdep.h
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/include/db_machdep.h,v
retrieving revision 1.27
diff -p -u -r1.27 db_machdep.h
--- sys/arch/arm/include/db_machdep.h	1 Apr 2018 04:35:04 -0000	1.27
+++ sys/arch/arm/include/db_machdep.h	24 Nov 2020 07:36:42 -0000
@@ -39,6 +39,7 @@
 #include <sys/types.h>
 #include <uvm/uvm_extern.h>
 #include <arm/armreg.h>
+#include <arm/cdefs.h>
 #include <machine/frame.h>
 #include <machine/trap.h>
 
@@ -70,7 +71,11 @@ extern db_regs_t *ddb_regp;
 #define BKPT_INST	(GDB5_BREAKPOINT)
 #endif
 #define	BKPT_SIZE	(INSN_SIZE)		/* size of breakpoint inst */
+#ifdef __ARM_ARCH_BE8
+#define	BKPT_SET(inst, addr)	(bswap32(BKPT_INST))
+#else
 #define	BKPT_SET(inst, addr)	(BKPT_INST)
+#endif
 
 /*#define FIXUP_PC_AFTER_BREAK(regs)	((regs)->tf_pc -= BKPT_SIZE)*/
 
Index: sys/arch/arm/include/locore.h
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/include/locore.h,v
retrieving revision 1.34
diff -p -u -r1.34 locore.h
--- sys/arch/arm/include/locore.h	30 Oct 2020 18:54:36 -0000	1.34
+++ sys/arch/arm/include/locore.h	24 Nov 2020 07:37:07 -0000
@@ -202,7 +202,7 @@ read_insn(vaddr_t va, bool user_p)
 	} else {
 		insn = *(const uint32_t *)va;
 	}
-#if defined(__ARMEB__) && defined(_ARM_ARCH_7)
+#ifdef _ARM_ARCH_BE8
 	insn = bswap32(insn);
 #endif
 	return insn;
@@ -232,7 +232,7 @@ read_thumb_insn(vaddr_t va, bool user_p)
 	} else {
 		insn = *(const uint16_t *)va;
 	}
-#if defined(__ARMEB__) && defined(_ARM_ARCH_7)
+#ifdef _ARM_ARCH_BE8
 	insn = bswap16(insn);
 #endif
 	return insn;
Index: sys/arch/arm/include/ptrace.h
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/include/ptrace.h,v
retrieving revision 1.15
diff -p -u -r1.15 ptrace.h
--- sys/arch/arm/include/ptrace.h	18 Jun 2019 21:18:12 -0000	1.15
+++ sys/arch/arm/include/ptrace.h	24 Nov 2020 07:37:44 -0000
@@ -31,6 +31,8 @@
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <arm/cdefs.h>
+
 /*
  * arm-dependent ptrace definitions
  */
@@ -67,12 +69,17 @@
 
 #define PTRACE_ILLEGAL_ASM	__asm __volatile ("udf #0" : : : "memory")
 
-#ifdef __ARMEB__
+#if defined(__ARMEL__) || defined(_ARM_ARCH_BE8)
 #define PTRACE_BREAKPOINT	((const uint8_t[]) { 0xfe, 0xde, 0xff, 0xe7 })
-#define PTRACE_BREAKPOINT_INSN	0xfedeffe7
 #else
 #define PTRACE_BREAKPOINT	((const uint8_t[]) { 0xe7, 0xff, 0xde, 0xfe })
+#endif
+
+#ifdef _ARM_ARCH_BE8
+#define PTRACE_BREAKPOINT_INSN	0xfedeffe7
+#else
 #define PTRACE_BREAKPOINT_INSN	0xe7ffdefe
 #endif
+
 #define PTRACE_BREAKPOINT_ASM	__asm __volatile (".word " ___STRING(PTRACE_BREAKPOINT_INSN) )
 #define PTRACE_BREAKPOINT_SIZE	4
Index: sys/arch/arm/include/trap.h
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/include/trap.h,v
retrieving revision 1.9
diff -p -u -r1.9 trap.h
--- sys/arch/arm/include/trap.h	15 Mar 2014 05:54:20 -0000	1.9
+++ sys/arch/arm/include/trap.h	24 Nov 2020 07:38:01 -0000
@@ -38,6 +38,8 @@
  * Various trap definitions
  */
 
+#include <arm/cdefs.h>
+
 /*
  * Instructions used for breakpoints.
  *
@@ -70,7 +72,11 @@
 #define DTRACE_BREAKPOINT_MASK	0xfffffff0
 #define DTRACE_IS_BREAKPOINT(insn)	((insn & DTRACE_BREAKPOINT_MASK) == DTRACE_BREAKPOINT)
 
+#ifdef _ARM_ARCH_BE8
+#define KBPT_ASM		".word 0xfedeffe7"
+#else
 #define KBPT_ASM		".word 0xe7ffdefe"
+#endif
 
 #define USER_BREAKPOINT		GDB_BREAKPOINT