Index: sys/arch/evbarm/conf/MARVELL_NAS =================================================================== RCS file: /home/netbsd/src/sys/arch/evbarm/conf/MARVELL_NAS,v retrieving revision 1.41 diff -p -u -r1.41 MARVELL_NAS --- sys/arch/evbarm/conf/MARVELL_NAS 27 Sep 2020 13:48:50 -0000 1.41 +++ sys/arch/evbarm/conf/MARVELL_NAS 25 Aug 2021 12:35:06 -0000 @@ -53,8 +53,8 @@ file-system HFS # experimental - Apple # File system options options QUOTA # legacy UFS quotas options QUOTA2 # new, in-filesystem UFS quotas -#options DISKLABEL_EI # disklabel Endian Independent support -#options FFS_EI # FFS Endian Independent support +options DISKLABEL_EI # disklabel Endian Independent support +options FFS_EI # FFS Endian Independent support options WAPBL # File system journaling support # Note that UFS_DIRHASH is suspected of causing kernel memory corruption. # It is not recommended for general use. Index: sys/arch/arm/marvell/armadaxp.c =================================================================== RCS file: /home/netbsd/src/sys/arch/arm/marvell/armadaxp.c,v retrieving revision 1.23 diff -p -u -r1.23 armadaxp.c --- sys/arch/arm/marvell/armadaxp.c 30 Oct 2020 18:54:36 -0000 1.23 +++ sys/arch/arm/marvell/armadaxp.c 25 Aug 2021 02:19:57 -0000 @@ -86,7 +86,7 @@ bus_space_handle_t mpic_cpu_handle; static bus_space_handle_t mpic_handle, l2_handle; int l2cache_state = 0; int iocc_state = 0; -#define read_miscreg(r) (*(volatile uint32_t *)(misc_base + (r))) +#define read_miscreg(r) le32toh(*(volatile uint32_t *)(misc_base + (r))) vaddr_t misc_base; vaddr_t armadaxp_l2_barrier_reg; Index: sys/arch/arm/marvell/dove.c =================================================================== RCS file: /home/netbsd/src/sys/arch/arm/marvell/dove.c,v retrieving revision 1.1 diff -p -u -r1.1 dove.c --- sys/arch/arm/marvell/dove.c 7 Jan 2017 16:19:28 -0000 1.1 +++ sys/arch/arm/marvell/dove.c 25 Aug 2021 02:20:20 -0000 @@ -61,7 +61,7 @@ __KERNEL_RCSID(0, "$NetBSD: dove.c,v 1.1 bus_space_write_4((sc)->sc_iot, (sc)->sc_pmch, (o), (v)) #else vaddr_t pmu_base = -1; -#define READ_PMUREG(sc, o) (*(volatile uint32_t *)(pmu_base + (o))) +#define READ_PMUREG(sc, o) le32toh(*(volatile uint32_t *)(pmu_base + (o))) #endif static void dove_intr_init(void); @@ -279,8 +279,8 @@ dove_getclks(bus_addr_t iobase) #define MHz * 1000 * 1000 - val = *(volatile uint32_t *)(iobase + DOVE_MISC_BASE + - DOVE_MISC_SAMPLE_AT_RESET0); + val = le32toh(*(volatile uint32_t *)(iobase + DOVE_MISC_BASE + + DOVE_MISC_SAMPLE_AT_RESET0)); switch (val & 0x01800000) { case 0x00000000: mvTclk = 166 MHz; break; Index: sys/arch/arm/marvell/kirkwood.c =================================================================== RCS file: /home/netbsd/src/sys/arch/arm/marvell/kirkwood.c,v retrieving revision 1.10 diff -p -u -r1.10 kirkwood.c --- sys/arch/arm/marvell/kirkwood.c 7 Jan 2017 16:19:28 -0000 1.10 +++ sys/arch/arm/marvell/kirkwood.c 25 Aug 2021 02:20:31 -0000 @@ -244,8 +244,8 @@ kirkwood_getclks(vaddr_t iobase) else /* 166MHz */ mvTclk = 166666667; - reg = *(volatile uint32_t *)(iobase + KIRKWOOD_MPP_BASE + - KIRKWOOD_MPP_SAMPLE_AT_RESET); + reg = le32toh(*(volatile uint32_t *)(iobase + KIRKWOOD_MPP_BASE + + KIRKWOOD_MPP_SAMPLE_AT_RESET)); if (model == MARVELL_KIRKWOOD_88F6180) { switch (reg & 0x0000001c) { case 0x00000014: mvPclk = 600 MHz; break; Index: sys/arch/arm/marvell/mv78xx0.c =================================================================== RCS file: /home/netbsd/src/sys/arch/arm/marvell/mv78xx0.c,v retrieving revision 1.2 diff -p -u -r1.2 mv78xx0.c --- sys/arch/arm/marvell/mv78xx0.c 7 Jan 2017 16:19:28 -0000 1.2 +++ sys/arch/arm/marvell/mv78xx0.c 25 Aug 2021 02:25:18 -0000 @@ -214,14 +214,16 @@ mv78xx0_getclks(vaddr_t iobase) #define MHz * 1000 * 1000 - reg = *(volatile uint32_t *)(iobase + MV78XX0_SAMPLE_AT_RESET_HIGH); + reg = le32toh(*(volatile uint32_t *)(iobase + + MV78XX0_SAMPLE_AT_RESET_HIGH)); switch (reg & 0x180) { case 0x000: mvTclk = 166666667; break; case 0x080: mvTclk = 200 MHz; break; default: mvTclk = 200 MHz; break; } - reg = *(volatile uint32_t *)(iobase + MV78XX0_SAMPLE_AT_RESET_LOW); + reg = le32toh(*(volatile uint32_t *)(iobase + + MV78XX0_SAMPLE_AT_RESET_LOW)); switch (reg & 0x0e0) { case 0x020: mvSysclk = 200 MHz; break; Index: sys/arch/arm/marvell/mvsoc.c =================================================================== RCS file: /home/netbsd/src/sys/arch/arm/marvell/mvsoc.c,v retrieving revision 1.31 diff -p -u -r1.31 mvsoc.c --- sys/arch/arm/marvell/mvsoc.c 7 Aug 2021 16:18:44 -0000 1.31 +++ sys/arch/arm/marvell/mvsoc.c 25 Aug 2021 02:36:11 -0000 @@ -92,13 +92,13 @@ static vaddr_t com_base; static inline uint32_t uart_read(bus_size_t o) { - return *(volatile uint32_t *)(com_base + (o << 2)); + return le32toh(*(volatile uint32_t *)(com_base + (o << 2))); } static inline void uart_write(bus_size_t o, uint32_t v) { - *(volatile uint32_t *)(com_base + (o << 2)) = v; + *(volatile uint32_t *)(com_base + (o << 2)) = htole32(v); } static int @@ -1195,21 +1195,21 @@ mvsoc_model(void) KASSERT(regbase != 0xffffffff); - reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); + reg = le32toh(*(volatile uint32_t *)(pex_base + PCI_ID_REG)); model = PCI_PRODUCT(reg); #if defined(ORION) if (model == PCI_PRODUCT_MARVELL_88F5182) { - reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + - ORION_PMI_SAMPLE_AT_RESET); + reg = le32toh(*(volatile uint32_t *)(regbase + ORION_PMI_BASE + + ORION_PMI_SAMPLE_AT_RESET)); if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) model = PCI_PRODUCT_MARVELL_88F5082; } #endif #if defined(KIRKWOOD) if (model == PCI_PRODUCT_MARVELL_88F6281) { - reg = *(volatile uint32_t *)(regbase + KIRKWOOD_MISC_BASE + - KIRKWOOD_MISC_DEVICEID); + reg = le32toh(*(volatile uint32_t *)(regbase + + KIRKWOOD_MISC_BASE + KIRKWOOD_MISC_DEVICEID)); if (reg == 1) /* 88F6192 is 1 */ model = MARVELL_KIRKWOOD_88F6192; } @@ -1226,7 +1226,7 @@ mvsoc_rev(void) KASSERT(regbase != 0xffffffff); - reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); + reg = le32toh(*(volatile uint32_t *)(pex_base + PCI_CLASS_REG)); rev = PCI_REVISION(reg); return rev; @@ -1311,10 +1311,11 @@ mvsoc_target_ddr(uint32_t attr, uint32_t aprint_error("unknwon ATTR: 0x%x", attr); return -1; } - sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); + sizereg = le32toh(*(volatile uint32_t *)(dsc_base + + MVSOC_DSC_CSSR(cs))); if (sizereg & MVSOC_DSC_CSSR_WINEN) { - baseaddrreg = - *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSBAR(cs)); + baseaddrreg = le32toh(*(volatile uint32_t *)(dsc_base + + MVSOC_DSC_CSBAR(cs))); if (base != NULL) *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; @@ -1401,7 +1402,7 @@ mvsoc_target_axi(int tag, uint32_t *base aprint_error("unknwon TAG: 0x%x", tag); return -1; } - val = *(volatile uint32_t *)(regbase + MVSOC_AXI_MMAP1(cs)); + val = le32toh(*(volatile uint32_t *)(regbase + MVSOC_AXI_MMAP1(cs))); if (val & MVSOC_AXI_MMAP1_VALID) { if (base != NULL) *base = MVSOC_AXI_MMAP1_STARTADDRESS(val); Index: sys/arch/arm/marvell/mvsoc_space.c =================================================================== RCS file: /home/netbsd/src/sys/arch/arm/marvell/mvsoc_space.c,v retrieving revision 1.10 diff -p -u -r1.10 mvsoc_space.c --- sys/arch/arm/marvell/mvsoc_space.c 16 Mar 2018 17:56:32 -0000 1.10 +++ sys/arch/arm/marvell/mvsoc_space.c 4 Aug 2021 06:53:52 -0000 @@ -42,6 +42,11 @@ __KERNEL_RCSID(0, "$NetBSD: mvsoc_space. #include #include +#ifdef __ARMEB__ +#define NSWAP(n) n ## _swap +#else +#define NSWAP(n) n +#endif /* Proto types for all the bus_space structure functions */ bs_protos(mvsoc); @@ -52,75 +57,75 @@ bs_protos(bs_notimpl); #define MVSOC_BUS_SPACE_NORMAL_FUNCS \ /* read (single) */ \ .bs_r_1 = generic_bs_r_1, \ - .bs_r_2 = generic_armv4_bs_r_2, \ - .bs_r_4 = generic_bs_r_4, \ + .bs_r_2 = NSWAP(generic_armv4_bs_r_2), \ + .bs_r_4 = NSWAP(generic_bs_r_4), \ .bs_r_8 = bs_notimpl_bs_r_8, \ \ /* read multiple */ \ .bs_rm_1 = generic_bs_rm_1, \ - .bs_rm_2 = generic_armv4_bs_rm_2, \ - .bs_rm_4 = generic_bs_rm_4, \ + .bs_rm_2 = NSWAP(generic_armv4_bs_rm_2),\ + .bs_rm_4 = NSWAP(generic_bs_rm_4), \ .bs_rm_8 = bs_notimpl_bs_rm_8, \ \ /* read region */ \ .bs_rr_1 = generic_bs_rr_1, \ - .bs_rr_2 = generic_armv4_bs_rr_2, \ - .bs_rr_4 = generic_bs_rr_4, \ + .bs_rr_2 = NSWAP(generic_armv4_bs_rr_2),\ + .bs_rr_4 = NSWAP(generic_bs_rr_4), \ .bs_rr_8 = bs_notimpl_bs_rr_8, \ \ /* write (single) */ \ .bs_w_1 = generic_bs_w_1, \ - .bs_w_2 = generic_armv4_bs_w_2, \ - .bs_w_4 = generic_bs_w_4, \ + .bs_w_2 = NSWAP(generic_armv4_bs_w_2), \ + .bs_w_4 = NSWAP(generic_bs_w_4), \ .bs_w_8 = bs_notimpl_bs_w_8, \ \ /* write multiple */ \ .bs_wm_1 = generic_bs_wm_1, \ - .bs_wm_2 = generic_armv4_bs_wm_2, \ - .bs_wm_4 = generic_bs_wm_4, \ + .bs_wm_2 = NSWAP(generic_armv4_bs_wm_2),\ + .bs_wm_4 = NSWAP(generic_bs_wm_4), \ .bs_wm_8 = bs_notimpl_bs_wm_8, \ \ /* write region */ \ .bs_wr_1 = generic_bs_wr_1, \ - .bs_wr_2 = generic_armv4_bs_wr_2, \ - .bs_wr_4 = generic_bs_wr_4, \ + .bs_wr_2 = NSWAP(generic_armv4_bs_wr_2),\ + .bs_wr_4 = NSWAP(generic_bs_wr_4), \ .bs_wr_8 = bs_notimpl_bs_wr_8 #define MVSOC_BUS_SPACE_STREAM_FUNCS \ /* read stream (single) */ \ .bs_r_1_s = generic_bs_r_1, \ - .bs_r_2_s = generic_armv4_bs_r_2, \ - .bs_r_4_s = generic_bs_r_4, \ + .bs_r_2_s = NSWAP(generic_armv4_bs_r_2),\ + .bs_r_4_s = NSWAP(generic_bs_r_4), \ .bs_r_8_s = bs_notimpl_bs_r_8, \ \ /* read multiple stream */ \ .bs_rm_1_s = generic_bs_rm_1, \ - .bs_rm_2_s = generic_armv4_bs_rm_2, \ - .bs_rm_4_s = generic_bs_rm_4, \ + .bs_rm_2_s = NSWAP(generic_armv4_bs_rm_2),\ + .bs_rm_4_s = NSWAP(generic_bs_rm_4), \ .bs_rm_8_s = bs_notimpl_bs_rm_8, \ \ /* read region stream */ \ .bs_rr_1_s = generic_bs_rr_1, \ - .bs_rr_2_s = generic_armv4_bs_rr_2, \ - .bs_rr_4_s = generic_bs_rr_4, \ + .bs_rr_2_s = NSWAP(generic_armv4_bs_rr_2),\ + .bs_rr_4_s = NSWAP(generic_bs_rr_4), \ .bs_rr_8_s = bs_notimpl_bs_rr_8, \ \ /* write stream (single) */ \ .bs_w_1_s = generic_bs_w_1, \ - .bs_w_2_s = generic_armv4_bs_w_2, \ - .bs_w_4_s = generic_bs_w_4, \ + .bs_w_2_s = NSWAP(generic_armv4_bs_w_2),\ + .bs_w_4_s = NSWAP(generic_bs_w_4, \ .bs_w_8_s = bs_notimpl_bs_w_8, \ \ /* write multiple stream */ \ .bs_wm_1_s = generic_bs_wm_1, \ - .bs_wm_2_s = generic_armv4_bs_wm_2, \ - .bs_wm_4_s = generic_bs_wm_4, \ + .bs_wm_2_s = NSWAP(generic_armv4_bs_wm_2),\ + .bs_wm_4_s = NSWAP(generic_bs_wm_4), \ .bs_wm_8_s = bs_notimpl_bs_wm_8, \ \ /* write region stream */ \ .bs_wr_1_s = generic_bs_wr_1, \ - .bs_wr_2_s = generic_armv4_bs_wr_2, \ - .bs_wr_4_s = generic_bs_wr_4, \ + .bs_wr_2_s = NSWAP(generic_armv4_bs_wr_2),\ + .bs_wr_4_s = NSWAP(generic_bs_wr_4), \ .bs_wr_8_s = bs_notimpl_bs_wr_8 #define MVSOC_BUS_SPACE_DEFAULT_FUNCS \ @@ -130,7 +135,7 @@ bs_protos(bs_notimpl); .bs_subregion = mvsoc_bs_subregion, \ \ /* allocation/deallocation */ \ - .bs_alloc =mvsoc_bs_alloc, \ + .bs_alloc = mvsoc_bs_alloc, \ .bs_free = mvsoc_bs_free, \ \ /* get kernel virtual address */ \ @@ -152,8 +157,8 @@ bs_protos(bs_notimpl); \ /* set region */ \ .bs_sr_1 = bs_notimpl_bs_sr_1, \ - .bs_sr_2 = generic_armv4_bs_sr_2, \ - .bs_sr_4 = generic_bs_sr_4, \ + .bs_sr_2 = NSWAP(generic_armv4_bs_sr_2),\ + .bs_sr_4 = NSWAP(generic_bs_sr_4), \ .bs_sr_8 = bs_notimpl_bs_sr_8, \ \ /* copy */ \ Index: sys/arch/arm/marvell/mvsocvar.h =================================================================== RCS file: /home/netbsd/src/sys/arch/arm/marvell/mvsocvar.h,v retrieving revision 1.12 diff -p -u -r1.12 mvsocvar.h --- sys/arch/arm/marvell/mvsocvar.h 10 Mar 2017 15:44:24 -0000 1.12 +++ sys/arch/arm/marvell/mvsocvar.h 25 Aug 2021 02:23:47 -0000 @@ -48,8 +48,10 @@ extern int gpp_npins, gpp_irqbase; extern struct bus_space mvsoc_bs_tag; extern struct arm32_bus_dma_tag mvsoc_bus_dma_tag; -#define read_mlmbreg(o) (*(volatile uint32_t *)(mlmb_base + (o))) -#define write_mlmbreg(o, v) (*(volatile uint32_t *)(mlmb_base + (o)) = (v)) +#define read_mlmbreg(o) \ + le32toh(*(volatile uint32_t *)(mlmb_base + (o))) +#define write_mlmbreg(o, v) \ + (*(volatile uint32_t *)(mlmb_base + (o)) = htole32(v)) void mvsoc_bootstrap(bus_addr_t); uint16_t mvsoc_model(void); Index: sys/arch/arm/marvell/orion.c =================================================================== RCS file: /home/netbsd/src/sys/arch/arm/marvell/orion.c,v retrieving revision 1.6 diff -p -u -r1.6 orion.c --- sys/arch/arm/marvell/orion.c 7 Jan 2017 16:19:28 -0000 1.6 +++ sys/arch/arm/marvell/orion.c 25 Aug 2021 02:23:56 -0000 @@ -224,8 +224,8 @@ orion_getclks(vaddr_t iobase) tclk_shift = 8; } - reg = *(volatile uint32_t *)(iobase + ORION_PMI_BASE + - ORION_PMI_SAMPLE_AT_RESET); + reg = le32toh(*(volatile uint32_t *)(iobase + ORION_PMI_BASE + + ORION_PMI_SAMPLE_AT_RESET)); armddrclk = (reg >> armddrclk_shift) & ORION_PMISMPL_ARMDDRCLK_MASK; if (model == PCI_PRODUCT_MARVELL_88F5281) if (reg & ORION_PMISMPL_ARMDDRCLK_H_MASK) Index: sys/arch/evbarm/marvell/marvell_machdep.c =================================================================== RCS file: /home/netbsd/src/sys/arch/evbarm/marvell/marvell_machdep.c,v retrieving revision 1.36 diff -p -u -r1.36 marvell_machdep.c --- sys/arch/evbarm/marvell/marvell_machdep.c 16 Jul 2019 14:41:47 -0000 1.36 +++ sys/arch/evbarm/marvell/marvell_machdep.c 25 Aug 2021 02:18:56 -0000 @@ -208,7 +208,8 @@ armadaxp_system_reset(void) { extern vaddr_t misc_base; -#define write_miscreg(r, v) (*(volatile uint32_t *)(misc_base + (r)) = (v)) +#define write_miscreg(r, v) \ + (*(volatile uint32_t *)(misc_base + (r)) = htole32(v)) /* Unmask soft reset */ write_miscreg(ARMADAXP_MISC_RSTOUTNMASKR, Index: sys/arch/evbarm/marvell/marvell_start.S =================================================================== RCS file: /home/netbsd/src/sys/arch/evbarm/marvell/marvell_start.S,v retrieving revision 1.10 diff -p -u -r1.10 marvell_start.S --- sys/arch/evbarm/marvell/marvell_start.S 16 Oct 2018 11:28:30 -0000 1.10 +++ sys/arch/evbarm/marvell/marvell_start.S 25 Aug 2021 15:09:09 -0000 @@ -104,6 +104,25 @@ _C_LABEL(marvell_start): * in VA 0xc0200000.. */ +#ifdef __ARMEB__ + /* + * u-boot is running in little-endian mode. Therefore, we need to + * encode first few instructions in the opposite byte order. + */ + + /* Turn on CPU_CONTROL_BEND_ENABLE bit. */ + .word 0x104f11ee /* mrc p15, 0, r4, c1, c0, 0 */ + .word 0x804084e3 /* orr r4, r4, #CPU_CONTROL_BEND_ENABLE */ + .word 0x104f01ee /* mcr p15, 0, r4, c1, c0, 0 */ + + /* Flush prefetch buffer. */ + .word 0x0000a0e1 /* nop */ + .word 0x0000a0e1 /* nop */ + .word 0x0000a0e1 /* nop */ + + CPWAIT(r4) +#endif + /* Check cores */ mrc p15, 0, r4, c0, c0, 0 and r4, r4, #CPU_ID_CPU_MASK Index: sys/dev/marvell/if_mvgbe.c =================================================================== RCS file: /home/netbsd/src/sys/dev/marvell/if_mvgbe.c,v retrieving revision 1.61 diff -p -u -r1.61 if_mvgbe.c --- sys/dev/marvell/if_mvgbe.c 7 Aug 2021 16:19:13 -0000 1.61 +++ sys/dev/marvell/if_mvgbe.c 25 Aug 2021 13:37:32 -0000 @@ -1254,7 +1254,7 @@ mvgbe_init(struct ifnet *ifp) /* Set SDC register except IPGINT bits */ MVGBE_WRITE(sc, MVGBE_SDC, MVGBE_SDC_RXBSZ_16_64BITWORDS | -#if BYTE_ORDER == LITTLE_ENDIAN +#ifndef MVGBE_BIG_ENDIAN MVGBE_SDC_BLMR | /* Big/Little Endian Receive Mode: No swap */ MVGBE_SDC_BLMT | /* Big/Little Endian Transmit Mode: No swap */ #endif @@ -1517,12 +1517,12 @@ mvgbe_init_rx_ring(struct mvgbe_softc *s cd->mvgbe_rx_chain[i].mvgbe_next = &cd->mvgbe_rx_chain[0]; rd->mvgbe_rx_ring[i].nextdescptr = - MVGBE_RX_RING_ADDR(sc, 0); + H2MVGBE32(MVGBE_RX_RING_ADDR(sc, 0)); } else { cd->mvgbe_rx_chain[i].mvgbe_next = &cd->mvgbe_rx_chain[i + 1]; rd->mvgbe_rx_ring[i].nextdescptr = - MVGBE_RX_RING_ADDR(sc, i + 1); + H2MVGBE32(MVGBE_RX_RING_ADDR(sc, i + 1)); } } @@ -1557,14 +1557,15 @@ mvgbe_init_tx_ring(struct mvgbe_softc *s cd->mvgbe_tx_chain[i].mvgbe_next = &cd->mvgbe_tx_chain[0]; rd->mvgbe_tx_ring[i].nextdescptr = - MVGBE_TX_RING_ADDR(sc, 0); + H2MVGBE32(MVGBE_TX_RING_ADDR(sc, 0)); } else { cd->mvgbe_tx_chain[i].mvgbe_next = &cd->mvgbe_tx_chain[i + 1]; rd->mvgbe_tx_ring[i].nextdescptr = - MVGBE_TX_RING_ADDR(sc, i + 1); + H2MVGBE32(MVGBE_TX_RING_ADDR(sc, i + 1)); } - rd->mvgbe_tx_ring[i].cmdsts = MVGBE_BUFFER_OWNED_BY_HOST; + rd->mvgbe_tx_ring[i].cmdsts = + H2MVGBE32(MVGBE_BUFFER_OWNED_BY_HOST); } sc->sc_cdata.mvgbe_tx_prod = 0; @@ -1629,9 +1630,10 @@ mvgbe_newbuf(struct mvgbe_softc *sc, int r = c->mvgbe_desc; c->mvgbe_mbuf = m_new; offset = (vaddr_t)m_new->m_data - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf; - r->bufptr = dmamap->dm_segs[0].ds_addr + offset; + r->bufptr = H2MVGBE32(dmamap->dm_segs[0].ds_addr + offset); r->bufsize = MVGBE_JLEN & ~MVGBE_RXBUF_MASK; - r->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT; + r->cmdsts = + H2MVGBE32(MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT); /* Invalidate RX buffer */ bus_dmamap_sync(sc->sc_dmat, dmamap, offset, r->bufsize, @@ -1873,10 +1875,10 @@ do_defrag: for (i = 0; i < txmap->dm_nsegs; i++) { f = &sc->sc_rdata->mvgbe_tx_ring[current]; - f->bufptr = txseg[i].ds_addr; - f->bytecnt = txseg[i].ds_len; + f->bufptr = H2MVGBE32(txseg[i].ds_addr); + f->bytecnt = H2MVGBE16(txseg[i].ds_len); if (i != 0) - f->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA; + f->cmdsts = H2MVGBE32(MVGBE_BUFFER_OWNED_BY_DMA); last = current; current = MVGBE_TX_RING_NEXT(current); } @@ -1897,21 +1899,21 @@ do_defrag: MVGBE_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */ } if (txmap->dm_nsegs == 1) - f->cmdsts = cmdsts | + f->cmdsts = H2MVGBE32(cmdsts | MVGBE_TX_ENABLE_INTERRUPT | MVGBE_TX_ZERO_PADDING | MVGBE_TX_FIRST_DESC | - MVGBE_TX_LAST_DESC; + MVGBE_TX_LAST_DESC); else { f = &sc->sc_rdata->mvgbe_tx_ring[first]; - f->cmdsts = cmdsts | MVGBE_TX_FIRST_DESC; + f->cmdsts = H2MVGBE32(cmdsts | MVGBE_TX_FIRST_DESC); f = &sc->sc_rdata->mvgbe_tx_ring[last]; - f->cmdsts = + f->cmdsts = H2MVGBE32( MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_TX_ENABLE_INTERRUPT | MVGBE_TX_ZERO_PADDING | - MVGBE_TX_LAST_DESC; + MVGBE_TX_LAST_DESC); /* Sync descriptors except first */ MVGBE_CDTXSYNC(sc, @@ -1926,7 +1928,7 @@ do_defrag: /* Finally, sync first descriptor */ sc->sc_rdata->mvgbe_tx_ring[first].cmdsts |= - MVGBE_BUFFER_OWNED_BY_DMA; + H2MVGBE32(MVGBE_BUFFER_OWNED_BY_DMA); MVGBE_CDTXSYNC(sc, *txidx, 1, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); @@ -1963,7 +1965,8 @@ mvgbe_rxeof(struct mvgbe_softc *sc) cur_rx = &sc->sc_rdata->mvgbe_rx_ring[idx]; - if ((cur_rx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == + rxstat = MVGBE2H32(cur_rx->cmdsts); + if ((rxstat & MVGBE_BUFFER_OWNED_MASK) == MVGBE_BUFFER_OWNED_BY_DMA) { /* Invalidate the descriptor -- it's not ready yet */ MVGBE_CDRXSYNC(sc, idx, BUS_DMASYNC_PREREAD); @@ -1971,7 +1974,7 @@ mvgbe_rxeof(struct mvgbe_softc *sc) break; } #ifdef DIAGNOSTIC - if ((cur_rx->cmdsts & + if ((rxstat & (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) != (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) panic( @@ -1985,8 +1988,7 @@ mvgbe_rxeof(struct mvgbe_softc *sc) m = cdata->mvgbe_rx_chain[idx].mvgbe_mbuf; cdata->mvgbe_rx_chain[idx].mvgbe_mbuf = NULL; - total_len = cur_rx->bytecnt - ETHER_CRC_LEN; - rxstat = cur_rx->cmdsts; + total_len = MVGBE2H16(cur_rx->bytecnt) - ETHER_CRC_LEN; bufsize = cur_rx->bufsize; cdata->mvgbe_rx_map[idx] = NULL; @@ -2083,6 +2085,7 @@ mvgbe_txeof(struct mvgbe_softc *sc) struct mvgbe_tx_desc *cur_tx; struct ifnet *ifp = &sc->sc_ethercom.ec_if; struct mvgbe_txmap_entry *entry; + uint32_t txstat; int idx; DPRINTFN(3, ("mvgbe_txeof\n")); @@ -2101,15 +2104,16 @@ mvgbe_txeof(struct mvgbe_softc *sc) if (mvgbe_debug >= 3) mvgbe_dump_txdesc(cur_tx, idx); #endif - if ((cur_tx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == + txstat = MVGBE2H32(cur_tx->cmdsts); + if ((txstat & MVGBE_BUFFER_OWNED_MASK) == MVGBE_BUFFER_OWNED_BY_DMA) { MVGBE_CDTXSYNC(sc, idx, 1, BUS_DMASYNC_PREREAD); break; } - if (cur_tx->cmdsts & MVGBE_TX_LAST_DESC) + if (txstat & MVGBE_TX_LAST_DESC) if_statinc(ifp, if_opackets); - if (cur_tx->cmdsts & MVGBE_ERROR_SUMMARY) { - int err = cur_tx->cmdsts & MVGBE_TX_ERROR_CODE_MASK; + if (txstat & MVGBE_ERROR_SUMMARY) { + int err = txstat & MVGBE_TX_ERROR_CODE_MASK; if (err == MVGBE_TX_LATE_COLLISION_ERROR) if_statinc(ifp, if_collisions); @@ -2256,18 +2260,18 @@ mvgbe_dump_txdesc(struct mvgbe_tx_desc * if (X) \ printf("txdesc[%d]." #X "=%#x\n", idx, X); -#if BYTE_ORDER == BIG_ENDIAN +#ifdef MVGBE_BIG_ENDIAN DESC_PRINT(desc->bytecnt); DESC_PRINT(desc->l4ichk); DESC_PRINT(desc->cmdsts); DESC_PRINT(desc->nextdescptr); DESC_PRINT(desc->bufptr); -#else /* LITTLE_ENDIAN */ - DESC_PRINT(desc->cmdsts); - DESC_PRINT(desc->l4ichk); - DESC_PRINT(desc->bytecnt); - DESC_PRINT(desc->bufptr); - DESC_PRINT(desc->nextdescptr); +#else + DESC_PRINT(MVGBE2H32(desc->cmdsts)); + DESC_PRINT(MVGBE2H16(desc->l4ichk)); + DESC_PRINT(MVGBE2H16(desc->bytecnt)); + DESC_PRINT(MVGBE2H32(desc->bufptr)); + DESC_PRINT(MVGBE2H32(desc->nextdescptr)); #endif #undef DESC_PRINT } Index: sys/dev/marvell/mvgbereg.h =================================================================== RCS file: /home/netbsd/src/sys/dev/marvell/mvgbereg.h,v retrieving revision 1.8 diff -p -u -r1.8 mvgbereg.h --- sys/dev/marvell/mvgbereg.h 23 Dec 2013 02:23:25 -0000 1.8 +++ sys/dev/marvell/mvgbereg.h 25 Aug 2021 15:00:42 -0000 @@ -27,6 +27,31 @@ #ifndef _MVGBEREG_H_ #define _MVGBEREG_H_ +/* + * For ARM, peripheral is configured to little-endian mode, even if + * CPU itself is in big-endian mode... + */ + +#if BYTE_ORDER == BIG_ENDIAN && !defined(__arm__) +#define MVGBE_BIG_ENDIAN +#endif + +/* + * ... therefore, we need byte-swapping descriptor fields for ARMEB. + */ + +#if BYTE_ORDER == BIG_ENDIAN && defined(__arm__) +#define H2MVGBE16(x) htole16(x) +#define H2MVGBE32(x) htole32(x) +#define MVGBE2H16(x) le16toh(x) +#define MVGBE2H32(x) le32toh(x) +#else +#define H2MVGBE16(x) (x) +#define H2MVGBE32(x) (x) +#define MVGBE2H16(x) (x) +#define MVGBE2H32(x) (x) +#endif + #define MVGBE_SIZE 0x4000 #define MVGBE_NWINDOW 6 @@ -758,13 +783,13 @@ * by the hardware. We'll just pad them out to that to make it easier. */ struct mvgbe_tx_desc { -#if BYTE_ORDER == BIG_ENDIAN +#ifdef MVGBE_BIG_ENDIAN uint16_t bytecnt; /* Descriptor buffer byte count */ uint16_t l4ichk; /* CPU provided TCP Checksum */ uint32_t cmdsts; /* Descriptor command status */ uint32_t nextdescptr; /* Next descriptor pointer */ uint32_t bufptr; /* Descriptor buffer pointer */ -#else /* LITTLE_ENDIAN */ +#else uint32_t cmdsts; /* Descriptor command status */ uint16_t l4ichk; /* CPU provided TCP Checksum */ uint16_t bytecnt; /* Descriptor buffer byte count */ @@ -775,13 +800,13 @@ struct mvgbe_tx_desc { } __packed; struct mvgbe_rx_desc { -#if BYTE_ORDER == BIG_ENDIAN +#ifdef MVGBE_BIG_ENDIAN uint16_t bytecnt; /* Descriptor buffer byte count */ uint16_t bufsize; /* Buffer size */ uint32_t cmdsts; /* Descriptor command status */ uint32_t nextdescptr; /* Next descriptor pointer */ uint32_t bufptr; /* Descriptor buffer pointer */ -#else /* LITTLE_ENDIAN */ +#else uint32_t cmdsts; /* Descriptor command status */ uint16_t bufsize; /* Buffer size */ uint16_t bytecnt; /* Descriptor buffer byte count */