Index: lib/libkvm/kvm_sparc64.c =================================================================== RCS file: /cvsroot/src/lib/libkvm/kvm_sparc64.c,v retrieving revision 1.15 diff -u -r1.15 kvm_sparc64.c --- lib/libkvm/kvm_sparc64.c 20 Sep 2010 23:23:16 -0000 1.15 +++ lib/libkvm/kvm_sparc64.c 19 Feb 2014 19:10:43 -0000 @@ -65,6 +65,7 @@ #include #include #include +#include #include #include @@ -211,7 +212,7 @@ * XXXX -- We could support multiple page sizes. */ va = va & (kd->nbpg - 1); - data &= TLB_PA_MASK; + data &= SUN4U_TLB_PA_MASK; /* XXX handle sun4u/sun4v */ *pa = data + va; /* Index: sys/arch/sparc/stand/ofwboot/loadfile_machdep.c =================================================================== RCS file: /cvsroot/src/sys/arch/sparc/stand/ofwboot/loadfile_machdep.c,v retrieving revision 1.11 diff -u -r1.11 loadfile_machdep.c --- sys/arch/sparc/stand/ofwboot/loadfile_machdep.c 8 Dec 2013 14:41:28 -0000 1.11 +++ sys/arch/sparc/stand/ofwboot/loadfile_machdep.c 19 Feb 2014 19:11:21 -0000 @@ -341,7 +341,7 @@ DPRINTF(("mmu_mapin: 0x%lx:0x%x.0x%x\n", va, hi(pa), lo(pa))); - data = TSB_DATA(0, /* global */ + data = SUN4U_TSB_DATA(0, /* global */ PGSZ_4M, /* 4mb page */ pa, /* phys.address */ 1, /* privileged */ @@ -351,7 +351,7 @@ 1, /* valid */ 0 /* endianness */ ); - data |= TLB_L | TLB_CV; /* locked, virt.cache */ + data |= SUN4U_TLB_L | SUN4U_TLB_CV; /* locked, virt.cache */ dtlb_store[dtlb_slot].te_pa = pa; dtlb_store[dtlb_slot].te_va = va; @@ -634,7 +634,7 @@ continue; } - data = TSB_DATA(0, /* global */ + data = SUN4U_TSB_DATA(0, /* global */ PGSZ_4M, /* 4mb page */ dtlb_store[i].te_pa, /* phys.address */ 1, /* privileged */ @@ -644,7 +644,7 @@ 1, /* valid */ 0 /* endianness */ ); - data |= TLB_L | TLB_CV; /* locked, virt.cache */ + data |= SUN4U_TLB_L | SUN4U_TLB_CV; /* locked, virt.cache */ if (!writable_text) dtlb_replace(dtlb_store[i].te_va, hi(data), lo(data)); itlb_store[itlb_slot] = dtlb_store[i]; Index: sys/arch/sparc64/doc/TODO =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/doc/TODO,v retrieving revision 1.1 diff -u -r1.1 TODO --- sys/arch/sparc64/doc/TODO 25 Jan 2014 19:07:25 -0000 1.1 +++ sys/arch/sparc64/doc/TODO 19 Feb 2014 19:11:21 -0000 @@ -7,3 +7,6 @@ sun4v: - 64-bit kernel support - 32-bit kernel support +- libkvm +- ofwboot: tlb_init_sun4v() hardcodes number of slots to 64 +- sun4v_datatrap: missing implementation \ No newline at end of file Index: sys/arch/sparc64/include/cpu.h =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/include/cpu.h,v retrieving revision 1.109 diff -u -r1.109 cpu.h --- sys/arch/sparc64/include/cpu.h 9 Jan 2014 20:28:23 -0000 1.109 +++ sys/arch/sparc64/include/cpu.h 19 Feb 2014 19:11:21 -0000 @@ -381,6 +381,7 @@ void clearfpstate(void); uint64_t probeget(paddr_t, int, int); int probeset(paddr_t, int, int, uint64_t); +void setcputyp(int); #define write_all_windows() __asm volatile("flushw" : : ) #define write_user_windows() __asm volatile("flushw" : : ) Index: sys/arch/sparc64/include/param.h =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/include/param.h,v retrieving revision 1.52 diff -u -r1.52 param.h --- sys/arch/sparc64/include/param.h 16 Dec 2013 20:17:35 -0000 1.52 +++ sys/arch/sparc64/include/param.h 19 Feb 2014 19:11:21 -0000 @@ -228,7 +228,8 @@ #define mstohz(ms) ((ms + 0UL) * hz / 1000) #endif -extern int cputyp; +/* Keep this a const so compiler optimization is done */ +extern const int cputyp; #if defined (SUN4US) || defined (SUN4V) #define CPU_ISSUN4U (cputyp == CPU_SUN4U) Index: sys/arch/sparc64/include/pte.h =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/include/pte.h,v retrieving revision 1.24 diff -u -r1.24 pte.h --- sys/arch/sparc64/include/pte.h 16 Dec 2013 20:17:35 -0000 1.24 +++ sys/arch/sparc64/include/pte.h 19 Feb 2014 19:11:21 -0000 @@ -152,41 +152,41 @@ #define PGSZ_512K 2 #define PGSZ_4M 3 -#define PGSZ_SHIFT 61 -#define TLB_SZ(s) (((uint64_t)(s))< 0) { if (strcmp(buf, "sun4us") == 0) - cputyp = CPU_SUN4US; + setcputyp(CPU_SUN4US); else if (strcmp(buf, "sun4v") == 0) - cputyp = CPU_SUN4V; + setcputyp(CPU_SUN4V); } bi_howto = lookup_bootinfo(BTINFO_BOOTHOWTO); Index: sys/arch/sparc64/sparc64/genassym.cf =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/genassym.cf,v retrieving revision 1.72 diff -u -r1.72 genassym.cf --- sys/arch/sparc64/sparc64/genassym.cf 26 Jan 2014 20:12:32 -0000 1.72 +++ sys/arch/sparc64/sparc64/genassym.cf 19 Feb 2014 19:11:21 -0000 @@ -137,9 +137,10 @@ define PM_WIRED offsetof(struct pmap, pm_stats.wired_count) # the assembler doesn't grok C constants with LL suffix -define A_TLB_TSB_LOCK TLB_TSB_LOCK +define A_SUN4U_TLB_TSB_LOCK SUN4U_TLB_TSB_LOCK ifdef SUN4V define A_SUN4V_TLB_ACCESS SUN4V_TLB_ACCESS +define A_SUN4V_TLB_TSB_LOCK SUN4V_TLB_TSB_LOCK endif # CPU info structure Index: sys/arch/sparc64/sparc64/locore.s =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/locore.s,v retrieving revision 1.355 diff -u -r1.355 locore.s --- sys/arch/sparc64/sparc64/locore.s 31 Jan 2014 18:56:24 -0000 1.355 +++ sys/arch/sparc64/sparc64/locore.s 19 Feb 2014 19:11:22 -0000 @@ -166,6 +166,9 @@ .globl romtba romtba: POINTER 0 + .globl cputyp +cputyp: .word CPU_SUN4U ! Default to sun4u + _ALIGN .text @@ -1523,9 +1526,9 @@ 1: ldxa [%g6] ASI_PHYS_CACHED, %g4 brgez,pn %g4, winfix ! Entry invalid? Punt - or %g4, TTE_MODIFY|TTE_ACCESS|TTE_W, %g7 ! Update the modified bit + or %g4, SUN4U_TTE_MODIFY|SUN4U_TTE_ACCESS|SUN4U_TTE_W, %g7 ! Update the modified bit - btst TTE_REAL_W|TTE_W, %g4 ! Is it a ref fault? + btst SUN4U_TTE_REAL_W|SUN4U_TTE_W, %g4 ! Is it a ref fault? bz,pn %xcc, winfix ! No -- really fault #ifdef DEBUG /* Make sure we don't try to replace a kernel translation */ @@ -1550,7 +1553,7 @@ membar #StoreLoad cmp %g4, %g7 bne,pn %xcc, 1b - or %g4, TTE_MODIFY|TTE_ACCESS|TTE_W, %g4 ! Update the modified bit + or %g4, SUN4U_TTE_MODIFY|SUN4U_TTE_ACCESS|SUN4U_TTE_W, %g4 ! Update the modified bit stx %g1, [%g2] ! Update TSB entry tag mov SFSR, %g7 stx %g4, [%g2+8] ! Update TSB entry data @@ -1654,15 +1657,15 @@ 1: ldxa [%g6] ASI_PHYS_CACHED, %g4 brgez,pn %g4, data_nfo ! Entry invalid? Punt - or %g4, TTE_ACCESS, %g7 ! Update the access bit + or %g4, SUN4U_TTE_ACCESS, %g7 ! Update the access bit - btst TTE_ACCESS, %g4 ! Need to update access git? + btst SUN4U_TTE_ACCESS, %g4 ! Need to update access git? bne,pt %xcc, 1f nop casxa [%g6] ASI_PHYS_CACHED, %g4, %g7 ! and write it out cmp %g4, %g7 bne,pn %xcc, 1b - or %g4, TTE_ACCESS, %g4 ! Update the access bit + or %g4, SUN4U_TTE_ACCESS, %g4 ! Update the access bit 1: stx %g1, [%g2] ! Update TSB entry tag @@ -2431,18 +2434,18 @@ nop /* Check if it's an executable mapping. */ - andcc %g4, TTE_EXEC, %g0 + andcc %g4, SUN4U_TTE_EXEC, %g0 bz,pn %xcc, textfault nop - or %g4, TTE_ACCESS, %g7 ! Update accessed bit - btst TTE_ACCESS, %g4 ! Need to update access git? + or %g4, SUN4U_TTE_ACCESS, %g7 ! Update accessed bit + btst SUN4U_TTE_ACCESS, %g4 ! Need to update access git? bne,pt %xcc, 1f nop casxa [%g6] ASI_PHYS_CACHED, %g4, %g7 ! and store it cmp %g4, %g7 bne,pn %xcc, 1b - or %g4, TTE_ACCESS, %g4 ! Update accessed bit + or %g4, SUN4U_TTE_ACCESS, %g4 ! Update accessed bit 1: stx %g1, [%g2] ! Update TSB entry tag stx %g4, [%g2+8] ! Update TSB entry data @@ -3457,7 +3460,7 @@ #ifdef TRAPS_USE_IG ! This is for interrupt debugging wrpr %g0, PSTATE_KERN|PSTATE_IG, %pstate ! DEBUG -#endif +#endif /* * If this is a %tick or %stick softint, clear it then call * interrupt_vector. Only one of them should be enabled at any given @@ -4219,17 +4222,17 @@ */ #ifdef NO_VCACHE -#define TTE_DATABITS TTE_L|TTE_CP|TTE_P|TTE_W +#define SUN4U_TTE_DATABITS SUN4U_TTE_L|SUN4U_TTE_CP|SUN4U_TTE_P|SUN4U_TTE_W #else -#define TTE_DATABITS TTE_L|TTE_CP|TTE_CV|TTE_P|TTE_W +#define SUN4U_TTE_DATABITS SUN4U_TTE_L|SUN4U_TTE_CP|SUN4U_TTE_CV|SUN4U_TTE_P|SUN4U_TTE_W #endif ENTRY_NOPROFILE(cpu_initialize) /* for cosmetic reasons - nicer backtrace */ /* Cache the cputyp in %l6 for later user below */ - sethi %hi(_C_LABEL(cputyp)), %l6 - ld [%l6 + %lo(_C_LABEL(cputyp))], %l6 + sethi %hi(cputyp), %l6 + ld [%l6 + %lo(cputyp)], %l6 /* * Step 5: is no more. @@ -4279,7 +4282,7 @@ andn %l1, %l4, %l1 ! Mask the phys page number or %l2, %l1, %l1 ! Now take care of the high bits - or %l1, TTE_DATABITS, %l2 ! And low bits: L=1|CP=1|CV=?|E=0|P=1|W=1|G=0 + or %l1, SUN4U_TTE_DATABITS, %l2 ! And low bits: L=1|CP=1|CV=?|E=0|P=1|W=1|G=0 !! !! Now, map in the interrupt stack as context==0 @@ -4441,6 +4444,12 @@ retl rdpr %tba, %o0 +ENTRY(setcputyp) + sethi %hi(cputyp), %o1 ! Trash %o1 assuming this is ok + st %o0, [%o1 + %lo(cputyp)] + retl + nop + #ifdef MULTIPROCESSOR /* * cpu_mp_startup is called with: @@ -4468,7 +4477,7 @@ or %l4, 0xfff, %l4 ! We can just load this in 12 (of 13) bits andn %l1, %l4, %l1 ! Mask the phys page number or %l2, %l1, %l1 ! Now take care of the high bits - or %l1, TTE_DATABITS, %l2 ! And low bits: L=1|CP=1|CV=?|E=0|P=1|W=1|G=0 + or %l1, SUN4U_TTE_DATABITS, %l2 ! And low bits: L=1|CP=1|CV=?|E=0|P=1|W=1|G=0 /* * Now, map in the interrupt stack & cpu_info as context==0 @@ -5940,7 +5949,20 @@ !! %o5 = old TTE !! see if stats needs an update - set A_TLB_TSB_LOCK, %g5 +#ifdef SUN4V + sethi %hi(cputyp), %g5 + ld [%g5 + %lo(cputyp)], %g5 + cmp %g5, CPU_SUN4V + bne,pt %icc, 0f + nop + sethi %hh(A_SUN4V_TLB_TSB_LOCK), %g5 + sllx %g5, 32, %g5 + ba 1f + nop +0: +#endif + set A_SUN4U_TLB_TSB_LOCK, %g5 +1: xor %o2, %o5, %o3 ! %o3 - what changed brgez,pn %o3, 5f ! has resident changed? (we predict it has) Index: sys/arch/sparc64/sparc64/ofw_machdep.c =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/ofw_machdep.c,v retrieving revision 1.41 diff -u -r1.41 ofw_machdep.c --- sys/arch/sparc64/sparc64/ofw_machdep.c 7 Jan 2014 20:11:35 -0000 1.41 +++ sys/arch/sparc64/sparc64/ofw_machdep.c 19 Feb 2014 19:11:22 -0000 @@ -100,6 +100,7 @@ int prom_set_trap_table_sun4u(vaddr_t tba) { + prom_printf("prom_set_trap_table_sun4u()\n"); struct { cell_t name; cell_t nargs; @@ -121,6 +122,7 @@ int prom_set_trap_table_sun4v(vaddr_t tba, paddr_t mmfsa) { + prom_printf("prom_set_trap_table_sun4v()\n"); struct { cell_t name; cell_t nargs;