? sys/arch/sparc64/sparc64/traps_sun4v.s Index: sys/arch/sparc64/include/cpu.h =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/include/cpu.h,v retrieving revision 1.106 diff -u -r1.106 cpu.h --- sys/arch/sparc64/include/cpu.h 16 Dec 2013 20:17:35 -0000 1.106 +++ sys/arch/sparc64/include/cpu.h 3 Jan 2014 21:58:13 -0000 @@ -173,7 +173,13 @@ */ pte_t *ci_tsb_dmmu; pte_t *ci_tsb_immu; - + +#ifdef SUN4V + /* MMU Fault Status Area. Will be initialized to the physical + address of the bottom of the interrupt stack */ + paddr_t ci_mmfsa; +#endif + /* probe fault in PCI config space reads */ bool ci_pci_probe; bool ci_pci_fault; Index: sys/arch/sparc64/include/ctlreg.h =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/include/ctlreg.h,v retrieving revision 1.60 diff -u -r1.60 ctlreg.h --- sys/arch/sparc64/include/ctlreg.h 16 Dec 2013 20:17:35 -0000 1.60 +++ sys/arch/sparc64/include/ctlreg.h 3 Jan 2014 21:58:13 -0000 @@ -55,6 +55,8 @@ #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ +#define ASI_SCRATCHPAD 0x20 /* [4v] scratchpad registers */ + #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ Index: sys/arch/sparc64/include/sparc64.h =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/include/sparc64.h,v retrieving revision 1.11 diff -u -r1.11 sparc64.h --- sys/arch/sparc64/include/sparc64.h 20 Feb 2010 16:46:38 -0000 1.11 +++ sys/arch/sparc64/include/sparc64.h 3 Jan 2014 21:58:13 -0000 @@ -39,6 +39,9 @@ }; int prom_set_trap_table(vaddr_t); +#ifdef SUN4V +int prom_set_trap_table_sun4v(vaddr_t, paddr_t); +#endif paddr_t prom_vtop(vaddr_t); vaddr_t prom_claim_virt(vaddr_t, int); vaddr_t prom_alloc_virt(int, int); Index: sys/arch/sparc64/sparc64/cpu.c =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/cpu.c,v retrieving revision 1.106 diff -u -r1.106 cpu.c --- sys/arch/sparc64/sparc64/cpu.c 16 Dec 2013 20:17:35 -0000 1.106 +++ sys/arch/sparc64/sparc64/cpu.c 3 Jan 2014 21:58:13 -0000 @@ -179,6 +179,10 @@ cpi->ci_spinup = NULL; cpi->ci_paddr = pa0; cpi->ci_self = cpi; +#ifdef SUN4V + if ( CPU_ISSUN4V ) + cpi->ci_mmfsa = pa0; +#endif cpi->ci_node = cpu_node; cpi->ci_idepth = -1; memset(cpi->ci_intrpending, -1, sizeof(cpi->ci_intrpending)); Index: sys/arch/sparc64/sparc64/genassym.cf =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/genassym.cf,v retrieving revision 1.68 diff -u -r1.68 genassym.cf --- sys/arch/sparc64/sparc64/genassym.cf 28 Dec 2013 11:12:09 -0000 1.68 +++ sys/arch/sparc64/sparc64/genassym.cf 3 Jan 2014 21:58:13 -0000 @@ -163,6 +163,9 @@ define CI_CTXBUSY offsetof(struct cpu_info, ci_ctxbusy) define CI_TSB_DMMU offsetof(struct cpu_info, ci_tsb_dmmu) define CI_TSB_IMMU offsetof(struct cpu_info, ci_tsb_immu) +#ifdef SUN4V +define CI_MMFSA offsetof(struct cpu_info, ci_mmfsa) +#endif ifdef MULTIPROCESSOR define CI_IPIEVC offsetof(struct cpu_info, ci_ipi_evcnt[0].ev_count) endif Index: sys/arch/sparc64/sparc64/locore.s =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/locore.s,v retrieving revision 1.352 diff -u -r1.352 locore.s --- sys/arch/sparc64/sparc64/locore.s 29 Dec 2013 12:36:30 -0000 1.352 +++ sys/arch/sparc64/sparc64/locore.s 3 Jan 2014 21:58:13 -0000 @@ -95,6 +95,30 @@ #include "ksyms.h" +#ifdef SUN4V + +/* + * The UltraSPARC T1 has a "feature" where a LDXA/STXA to ASI_SCRATCHPAD + * registers may corrupt an unrelated integer register file register. + * To prevent this, it is required to have a non-store or NOP instruction + * before any LDXA/STXA to this register. + */ + +/* + * cpuinfo pa is located in scratchpad register 2 (0x10) + */ +#define GET_CPUINFO_PA(ci) \ + mov 0x10, ci ;\ + nop ;\ + ldxa [ci] ASI_SCRATCHPAD, ci + +#define GET_MMFSA(mmfsa) \ + GET_CPUINFO_PA(mmfsa) ;\ + add mmfsa, CI_MMFSA, mmfsa ;\ + ldxa [mmfsa] ASI_PHYS_CACHED, mmfsa + +#endif + #if 1 /* * Try to issue an elf note to ask the Solaris @@ -864,6 +888,44 @@ UTRAP(0x1f0); UTRAP(0x1f1); UTRAP(0x1f2); UTRAP(0x1f3); UTRAP(0x1f4); UTRAP(0x1f5); UTRAP(0x1f6); UTRAP(0x1f7) UTRAP(0x1f8); UTRAP(0x1f9); UTRAP(0x1fa); UTRAP(0x1fb); UTRAP(0x1fc); UTRAP(0x1fd); UTRAP(0x1fe); UTRAP(0x1ff) +#ifdef SUN4V + +/* Macros for sun4v traps */ + +/* FIXME debug only */ +sun4v_dummy_trap_entry: + ba sun4v_dummy_trap_entry + nop + + set 1f, %o0 + rdpr %tt, %o1 + call _C_LABEL(prom_printf) + nop + sir + .data +1: + .asciz "sun4v trap entry %x\n" + _ALIGN + .text + + .macro sun4v_trap_entry count + .rept \count + !ba,a,pt %xcc, slowtrap + ba,a,pt %xcc, sun4v_dummy_trap_entry + nop + .align 32 + .endr + .endm + +/* The actual trap base for sun4v */ + .align 0x8000 + .globl _C_LABEL(trapbase_sun4v) +_C_LABEL(trapbase_sun4v): + sun4v_trap_entry 512 ! trap level 0: 0x000-0x1ff + sun4v_trap_entry 512 ! trap level 1: 0x000-0x1ff + +#endif + #if 0 /* * If the cleanwin trap handler detects an overfow we come here. @@ -4179,9 +4241,25 @@ 1: /* set trap table */ +#ifdef SUN4V + cmp %l6, CPU_SUN4V + bne,pt %icc, 6f + nop + /* sun4v */ + set _C_LABEL(trapbase_sun4v), %l1 + GET_MMFSA(%o1) + call _C_LABEL(prom_set_trap_table_sun4v) ! Now we should be running 100% from our handlers + mov %l1, %o0 + + ba 7f + nop +6: +#endif + /* sun4u */ set _C_LABEL(trapbase), %l1 call _C_LABEL(prom_set_trap_table) ! Now we should be running 100% from our handlers mov %l1, %o0 +7: wrpr %l1, 0, %tba ! Make sure the PROM didn't foul up. /* @@ -4220,7 +4298,7 @@ /* * Call our startup routine. */ - + LDPTR [%l7 + CI_SPINUP], %o1 call %o1 ! Call routine Index: sys/arch/sparc64/sparc64/ofw_machdep.c =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/ofw_machdep.c,v retrieving revision 1.40 diff -u -r1.40 ofw_machdep.c --- sys/arch/sparc64/sparc64/ofw_machdep.c 9 Jul 2013 20:32:11 -0000 1.40 +++ sys/arch/sparc64/sparc64/ofw_machdep.c 3 Jan 2014 21:58:13 -0000 @@ -95,7 +95,7 @@ /* - * Point prom to our trap table. This stops the prom from mapping us. + * Point prom to our sun4u trap table. This stops the prom from mapping us. */ int prom_set_trap_table(vaddr_t tba) @@ -114,6 +114,31 @@ return openfirmware(&args); } +#ifdef SUN4V +/* + * Point prom to our sun4v trap table. This stops the prom from mapping us. + */ +int +prom_set_trap_table_sun4v(vaddr_t tba, paddr_t mmfsa) +{ + prom_printf("FIXME prom_set_trap_table_sun4v(%p, %p)\n", (void*)tba, (void*)mmfsa); + struct { + cell_t name; + cell_t nargs; + cell_t nreturns; + cell_t tba; + cell_t mmfsa; + } args; + + args.name = ADR2CELL("SUNW,set-trap-table"); + args.nargs = 2; + args.nreturns = 0; + args.tba = ADR2CELL(tba); + args.mmfsa = ADR2CELL(mmfsa); + return openfirmware(&args); +} +#endif + /* * Have the prom convert from virtual to physical addresses. * Index: sys/arch/sparc64/sparc64/pmap.c =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/pmap.c,v retrieving revision 1.284 diff -u -r1.284 pmap.c --- sys/arch/sparc64/sparc64/pmap.c 28 Dec 2013 11:08:56 -0000 1.284 +++ sys/arch/sparc64/sparc64/pmap.c 3 Jan 2014 21:58:14 -0000 @@ -854,7 +854,13 @@ prom_printf("Cannot allocate cpu_infos\n"); prom_halt(); } - +#ifdef SUN4V + if ( CPU_ISSUN4V ) { + /* Store physical address of cpuinfo for use in GET_CPUINFO_PA(). + Uses scratchpad register 2 (0x10) */ + stxa(0x10, ASI_SCRATCHPAD, cpu0paddr + (CPUINFO_VA - INTSTACK)); + } +#endif /* * Now the kernel text segment is in its final location we can try to * find out how much memory really is free. @@ -1112,7 +1118,7 @@ vmmap += PAGE_SIZE; /* Matchup virtual color for D$ */ intstk = vmmap; cpus = (struct cpu_info *)(intstk + CPUINFO_VA - INTSTACK); - + BDPRINTF(PDB_BOOT1, ("Inserting cpu_info into pmap_kernel() at %p\n", cpus)); @@ -1157,6 +1163,10 @@ cpus->ci_eintstack = NULL; cpus->ci_spinup = main; /* Call main when we're running. */ cpus->ci_paddr = cpu0paddr; +#ifdef SUN4V + if ( CPU_ISSUN4V ) + cpus->ci_mmfsa = cpu0paddr; +#endif cpus->ci_cpcb = (struct pcb *)u0va; cpus->ci_idepth = -1; memset(cpus->ci_intrpending, -1, sizeof(cpus->ci_intrpending)); @@ -3802,9 +3812,6 @@ panic("hv_mmu_map_perm_addr() failed - rc = %" PRId64 "\n", hv_rc); } - else { - memset((void *)INTSTACK, 0, 64 * KB); - } } void