Index: sys/arch/sparc64/sparc64/cache.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/cache.c,v
retrieving revision 1.8
diff -u -r1.8 cache.c
--- sys/arch/sparc64/sparc64/cache.c	6 Jun 2011 02:49:39 -0000	1.8
+++ sys/arch/sparc64/sparc64/cache.c	29 Dec 2014 18:25:08 -0000
@@ -75,6 +75,24 @@
 void    (*sp_dcache_flush_page)(paddr_t) = dcache_flush_page_us;
 #endif
 
+void	(*sp_tlb_flush_pte)(vaddr_t, int)	= sp_tlb_flush_pte_us;
+void	(*sp_tlb_flush_all)(void)		= sp_tlb_flush_all_us;
+
+static void
+sp_tlb_flush_pte_sun4v(vaddr_t va, int ctx)
+{
+	int64_t hv_rc;
+	hv_rc = hv_mmu_demap_page(va, ctx, MAP_DTLB|MAP_ITLB);
+	if ( hv_rc != H_EOK )
+		panic("hv_mmu_demap_page(%p,%d) failed - rc = %" PRIx64 "\n", (void*)va, ctx, hv_rc);
+}
+
+static void
+sp_tlb_flush_all_sun4v(void)
+{
+	panic("sp_tlb_flush_all_sun4v() not implemented yet");
+}
+
 void
 cache_setup_funcs(void)
 {
@@ -103,4 +121,16 @@
 		}
 #endif
 	}
+
+	/* Prepare sp_tlb_flush_* functions */
+	if (CPU_ISSUN4V) {
+		sp_tlb_flush_pte = sp_tlb_flush_pte_sun4v;
+		sp_tlb_flush_all = sp_tlb_flush_all_sun4v;
+	} else {
+		if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP()) {
+			sp_tlb_flush_pte = sp_tlb_flush_pte_usiii;
+			sp_tlb_flush_all = sp_tlb_flush_all_usiii;
+		}
+	}
+
 }
Index: sys/arch/sparc64/sparc64/cache.h
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/cache.h,v
retrieving revision 1.26
diff -u -r1.26 cache.h
--- sys/arch/sparc64/sparc64/cache.h	5 Nov 2014 13:50:50 -0000	1.26
+++ sys/arch/sparc64/sparc64/cache.h	29 Dec 2014 18:25:08 -0000
@@ -118,39 +118,13 @@
 void sp_tlb_flush_all_us(void);
 void sp_tlb_flush_all_usiii(void);
 
-static __inline__ void
-sp_tlb_flush_pte_sun4v(vaddr_t va, int ctx)
-{
-	int64_t hv_rc;
-	hv_rc = hv_mmu_demap_page(va, ctx, MAP_DTLB|MAP_ITLB);
-	if ( hv_rc != H_EOK )
-		panic("hv_mmu_demap_page(%p,%d) failed - rc = %" PRIx64 "\n", (void*)va, ctx, hv_rc);
-}
-
-static __inline__ void
-sp_tlb_flush_pte(vaddr_t va, int ctx)
-{
-	if (CPU_ISSUN4V)
-		sp_tlb_flush_pte_sun4v(va, ctx);
-	else if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP())
-		sp_tlb_flush_pte_usiii(va, ctx);
-	else
-		sp_tlb_flush_pte_us(va, ctx);
-}
-
-static __inline__ void
-sp_tlb_flush_all(void)
-{
-	if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP())
-		sp_tlb_flush_all_usiii();
-	else
-		sp_tlb_flush_all_us();
-}
 
 extern	void	(*dcache_flush_page)(paddr_t);
 extern	void	(*dcache_flush_page_cpuset)(paddr_t, sparc64_cpuset_t);
 extern	void	(*blast_dcache)(void);
 extern	void	(*blast_icache)(void);
+extern	void	(*sp_tlb_flush_pte)(vaddr_t, int);
+extern	void	(*sp_tlb_flush_all)(void);
 
 void cache_setup_funcs(void);