Index: sys/arch/sparc64/dev/fhc.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/dev/fhc.c,v
retrieving revision 1.3
diff -u -r1.3 fhc.c
--- sys/arch/sparc64/dev/fhc.c	18 Mar 2012 05:26:58 -0000	1.3
+++ sys/arch/sparc64/dev/fhc.c	7 May 2016 20:54:16 -0000
@@ -251,10 +251,7 @@
 	vec = ((sc->sc_ign << INTMAP_IGN_SHIFT) & INTMAP_IGN) |
 	    INTINO(ihandle);
 
-	ih = (struct intrhand *)
-		malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT);
-	if (ih == NULL)
-		return (NULL);
+	ih = intrhand_alloc();
 
 	ih->ih_ivec = ihandle;
 
Index: sys/arch/sparc64/dev/psycho.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/dev/psycho.c,v
retrieving revision 1.123
diff -u -r1.123 psycho.c
--- sys/arch/sparc64/dev/psycho.c	27 Nov 2015 00:36:58 -0000	1.123
+++ sys/arch/sparc64/dev/psycho.c	7 May 2016 20:54:16 -0000
@@ -707,8 +707,7 @@
 {
 	struct intrhand *ih;
 
-	ih = (struct intrhand *)malloc(sizeof(struct intrhand),
-		M_DEVBUF, M_NOWAIT);
+	ih = intrhand_alloc();
 	ih->ih_arg = sc;
 	ih->ih_map = mapper;
 	ih->ih_clr = clearer;
@@ -1273,9 +1272,7 @@
 	int ino;
 	long vec = INTVEC(ihandle);
 
-	ih = malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT);
-	if (ih == NULL)
-		return (NULL);
+	ih = intrhand_alloc();
 
 	ih->ih_ivec = ihandle;
 
Index: sys/arch/sparc64/dev/pyro.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/dev/pyro.c,v
retrieving revision 1.16
diff -u -r1.16 pyro.c
--- sys/arch/sparc64/dev/pyro.c	2 Oct 2015 05:22:52 -0000	1.16
+++ sys/arch/sparc64/dev/pyro.c	7 May 2016 20:54:16 -0000
@@ -580,9 +580,7 @@
 
 	ino |= INTVEC(ihandle);
 
-	ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT);
-	if (ih == NULL)
-		return (NULL);
+	ih = intrhand_alloc();
 
 	/* Register the map and clear intr registers */
 	ih->ih_map = intrmapptr;
Index: sys/arch/sparc64/dev/sbus.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/dev/sbus.c,v
retrieving revision 1.93
diff -u -r1.93 sbus.c
--- sys/arch/sparc64/dev/sbus.c	30 Jan 2012 04:25:15 -0000	1.93
+++ sys/arch/sparc64/dev/sbus.c	7 May 2016 20:54:16 -0000
@@ -254,8 +254,7 @@
 	iommu_init(name, &sc->sc_is, 0, -1);
 
 	/* Enable the over temp intr */
-	ih = (struct intrhand *)
-		malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT);
+	ih = intrhand_alloc();
 	ih->ih_map = &sc->sc_sysio->therm_int_map;
 	ih->ih_clr = NULL; /* &sc->sc_sysio->therm_clr_int; */
 	ih->ih_fun = sbus_overtemp;
@@ -508,10 +507,7 @@
 	int ipl;
 	long vec = pri; 
 
-	ih = (struct intrhand *)
-		malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT);
-	if (ih == NULL)
-		return (NULL);
+	ih = intrhand_alloc();
 
 	if ((vec & SBUS_INTR_COMPAT) != 0)
 		ipl = vec & ~SBUS_INTR_COMPAT;
Index: sys/arch/sparc64/dev/schizo.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/dev/schizo.c,v
retrieving revision 1.35
diff -u -r1.35 schizo.c
--- sys/arch/sparc64/dev/schizo.c	27 Nov 2015 09:34:36 -0000	1.35
+++ sys/arch/sparc64/dev/schizo.c	7 May 2016 20:54:16 -0000
@@ -588,10 +588,8 @@
 	DPRINTF(SDB_INTR, (" mapoff %" PRIx64 " clroff %" PRIx64 "\n",
 	    mapoff, clroff));
 
-	ih = (struct intrhand *)
-		kmem_alloc(sizeof(struct intrhand), KM_NOSLEEP);
-	if (ih == NULL)
-		return;
+	ih = intrhand_alloc();
+	
 	ih->ih_arg = arg;
 	intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh);
 	ih->ih_map = (uint64_t *)(uintptr_t)(intrregs + mapoff);
@@ -815,9 +813,7 @@
 	vec = INTVEC(ihandle);
 	ino = INTINO(vec);
 
-	ih = kmem_alloc(sizeof *ih, KM_NOSLEEP);
-	if (ih == NULL)
-		return (NULL);
+	ih = intrhand_alloc();
 
 	DPRINTF(SDB_INTR, ("\n%s: ihandle %x level %d fn %p arg %p\n", __func__,
 	    ihandle, level, handler, arg));
Index: sys/arch/sparc64/dev/vpci.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/dev/vpci.c,v
retrieving revision 1.6
diff -u -r1.6 vpci.c
--- sys/arch/sparc64/dev/vpci.c	27 Nov 2015 13:51:57 -0000	1.6
+++ sys/arch/sparc64/dev/vpci.c	7 May 2016 20:54:16 -0000
@@ -114,7 +114,7 @@
 static void * vpci_pci_intr_establish(pci_chipset_tag_t pc,
 				      pci_intr_handle_t ih, int level,
 				      int (*func)(void *), void *arg);
-
+void vpci_intr_ack(struct intrhand *);
 int vpci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
 int vpci_bus_map(bus_space_tag_t, bus_addr_t,
     bus_size_t, int, vaddr_t, bus_space_handle_t *);
@@ -596,9 +596,7 @@
 	ino |= INTVEC(ihandle);
 	DPRINTF(VDB_INTR, ("%s: ih %lx; level %d ino %#x\n", __func__, (u_long)ihandle, level, ino));
 
-	ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT);
-	if (ih == NULL)
-		return (NULL);
+	ih = intrhand_alloc();
 
 	ih->ih_ivec = ihandle;
 	ih->ih_fun = handler;
@@ -606,12 +604,44 @@
 	ih->ih_pil = level;
 	ih->ih_number = ino;
 	ih->ih_pending = 0;
-	
+	ih->ih_ack = vpci_intr_ack;
 	intr_establish(ih->ih_pil, level != IPL_VM, ih);
 
+	uint64_t sysino = INTVEC(ihandle);
+	DPRINTF(VDB_INTR, ("vpci_intr_establish(): sysino 0x%lx\n", sysino));
+
+	int err;
+
+	err = hv_intr_settarget(sysino, cpus->ci_cpuid);
+	if (err != H_EOK)
+		printf("hv_intr_settarget(%lu, %u) failed - err = %d\n", 
+		       (long unsigned int)sysino, cpus->ci_cpuid, err);
+
+	/* Clear pending interrupts. */
+	err = hv_intr_setstate(sysino, INTR_IDLE);
+	if (err != H_EOK)
+	  printf("hv_intr_setstate(%lu, INTR_IDLE) failed - err = %d\n", 
+		(long unsigned int)sysino, err);
+
+	err = hv_intr_setenabled(sysino, INTR_ENABLED);
+	if (err != H_EOK)
+	  printf("hv_intr_setenabled(%lu) failed - err = %d\n", 
+		(long unsigned int)sysino, err);
+
+	DPRINTF(VDB_INTR, ("%s() returning %p\n", __func__, ih));
 	return (ih);
 }
 
+void
+vpci_intr_ack(struct intrhand *ih)
+{
+	int err;
+	err = hv_intr_setstate(ih->ih_number, INTR_IDLE);
+	if (err != H_EOK)
+	  panic("%s(%u, INTR_IDLE) failed - err = %d\n", 
+		__func__, ih->ih_number, err);
+}
+
 static void *
 vpci_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
 	int (*func)(void *), void *arg)
Index: sys/arch/sparc64/include/cpu.h
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/include/cpu.h,v
retrieving revision 1.118
diff -u -r1.118 cpu.h
--- sys/arch/sparc64/include/cpu.h	7 Sep 2015 20:00:49 -0000	1.118
+++ sys/arch/sparc64/include/cpu.h	7 May 2016 20:54:16 -0000
@@ -361,6 +361,7 @@
 	struct intrhand		*ih_pending;	/* interrupt queued */
 	volatile uint64_t	*ih_map;	/* Interrupt map reg */
 	volatile uint64_t	*ih_clr;	/* clear interrupt reg */
+	void			(*ih_ack)(struct intrhand *); /* ack interrupt function */
 	struct evcnt		ih_cnt;		/* counter for vmstat */
 	uint32_t		ih_ivec;
 	char			ih_name[32];	/* name for the above */
@@ -372,6 +373,7 @@
 void	*sparc_softintr_establish(int, int (*)(void *), void *);
 void	sparc_softintr_schedule(void *);
 void	sparc_softintr_disestablish(void *);
+struct intrhand *intrhand_alloc(void);
 
 /* cpu.c */
 int	cpu_myid(void);
Index: sys/arch/sparc64/sparc64/genassym.cf
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/genassym.cf,v
retrieving revision 1.76
diff -u -r1.76 genassym.cf
--- sys/arch/sparc64/sparc64/genassym.cf	1 Apr 2015 18:38:30 -0000	1.76
+++ sys/arch/sparc64/sparc64/genassym.cf	7 May 2016 20:54:16 -0000
@@ -170,6 +170,7 @@
 define	CI_MMFSA	offsetof(struct cpu_info, ci_mmfsa)
 define	CI_TSB_DESC	offsetof(struct cpu_info, ci_tsb_desc)
 define	CI_CPUMQ	offsetof(struct cpu_info, ci_cpumq)
+define	CI_DEVMQ	offsetof(struct cpu_info, ci_devmq)
 ifdef MULTIPROCESSOR
 define	CI_IPIEVC	offsetof(struct cpu_info, ci_ipi_evcnt[0].ev_count)
 endif
@@ -254,6 +255,7 @@
 define	IH_NEXT		offsetof(struct intrhand, ih_next)
 define	IH_MAP		offsetof(struct intrhand, ih_map)
 define	IH_CLR		offsetof(struct intrhand, ih_clr)
+define	IH_ACK		offsetof(struct intrhand, ih_ack)
 define  IH_CNT		offsetof(struct intrhand, ih_cnt)
 	
 # mbuf fields of import
Index: sys/arch/sparc64/sparc64/intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/intr.c,v
retrieving revision 1.67
diff -u -r1.67 intr.c
--- sys/arch/sparc64/sparc64/intr.c	11 Aug 2012 21:50:09 -0000	1.67
+++ sys/arch/sparc64/sparc64/intr.c	7 May 2016 20:54:16 -0000
@@ -170,6 +170,22 @@
 #endif
 
 /*
+ * Allocate memory for interrupt handler.
+ * The allocated memory is initialized with zeros so 
+ * e.g. pointers in the intrhand structure are properly initialized.
+ * A valid pointer is always returned by the function.
+ */
+struct intrhand*
+intrhand_alloc(void)
+{
+	/* XXX use kmem_zalloc instead? kmem_zalloc(sizeof(struct intrhand), KM_NOSLEEP); */
+	struct intrhand *ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT|M_ZERO);
+	if (ih == NULL)
+		panic("%s: failed to allocate intrhand", __func__);
+	return ih;
+}
+
+/*
  * Attach an interrupt handler to the vector chain for the given level.
  * This is not possible if it has been taken away as a fast vector.
  */
Index: sys/arch/sparc64/sparc64/locore.s
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/locore.s,v
retrieving revision 1.390
diff -u -r1.390 locore.s
--- sys/arch/sparc64/sparc64/locore.s	9 Mar 2016 12:20:20 -0000	1.390
+++ sys/arch/sparc64/sparc64/locore.s	7 May 2016 20:54:16 -0000
@@ -1071,7 +1071,8 @@
 	HARDINT4V(15)						! 0x04f = level 15 interrupt
 	sun4v_trap_entry 44					! 0x050-0x07b
 	VTRAP(T_CPU_MONDO, sun4v_cpu_mondo)			! 0x07c = cpu mondo
-	sun4v_trap_entry 3					! 0x07d-0x07f
+	VTRAP(T_DEV_MONDO, sun4v_dev_mondo)			! 0x07d = dev mondo
+	sun4v_trap_entry 2					! 0x07e-0x07f
 	SPILL64(uspill8_sun4vt0,ASI_AIUS)			! 0x080 spill_0_normal -- used to save user windows in user mode
 	SPILL32(uspill4_sun4vt0,ASI_AIUS)			! 0x084 spill_1_normal
 	SPILLBOTH(uspill8_sun4vt0,uspill4_sun4vt0,ASI_AIUS)	! 0x088 spill_2_normal
@@ -3592,6 +3593,8 @@
 	 nop				! XXX spitfire bug?
 
 sun4v_cpu_mondo:
+! XXX Rework this when a UP kernel works - crash for now	
+	sir			
 	mov	0x3c0, %g1			 ! CPU Mondo Queue Head
 	ldxa	[%g1] ASI_QUEUE, %g2		 ! fetch index value for head
 	set	CPUINFO_VA, %g3
@@ -3616,7 +3619,45 @@
 	retry
 	NOTREACHED
 
-	
+sun4v_dev_mondo:
+	mov	0x3d0, %g1			! Dev Mondo Queue Head
+	ldxa	[%g1] ASI_QUEUE, %g2		! fetch index value
+	mov	0x3d8, %g1			! Dev Mondo Queue Tail
+	ldxa	[%g1] ASI_QUEUE, %g4		! fetch index value
+	cmp	%g2, %g4			! head = queue? 
+	bne,pt 	%xcc, 2f			! unsually not the case
+	 nop
+	retry					! unlikely, ingnore interrupt
+2:	
+	set	CPUINFO_VA, %g3			 ! fetch cpuinfo pa
+	LDPTR	[%g3 + CI_PADDR], %g3		 ! fetch intstack pa
+	set	CPUINFO_VA-INTSTACK, %g4	 ! offset to cpuinfo
+	add	%g4, %g3, %g3			 ! %g3 is now cpuifo
+	add	%g3, CI_DEVMQ, %g3		 ! calc offset to devmq
+	ldxa	[%g3] ASI_PHYS_CACHED, %g3	 ! fetch address of devmq
+	ldxa	[%g3 + %g2] ASI_PHYS_CACHED, %g5 !
+	add	%g2, 64, %g2			 ! each element is 64 bytes 		
+	and	%g2, 0x7ff, %g2			 ! assume 32 elements
+	mov	0x3d0, %g1			 ! Dev Mondo Queue Head
+	stxa	%g2, [%g1] ASI_QUEUE		 ! ajust head index value
+	membar	#Sync
+
+	cmp	%g5, MAXINTNUM			! out of bounds?
+	bgeu,pn	%xcc, 2f
+	 nop					! no just continue
+
+	sethi	%hi(_C_LABEL(intrlev)), %g3
+	or	%g3, %lo(_C_LABEL(intrlev)), %g3
+	sllx	%g5, 3, %g5		! Calculate entry number
+	ldx	[%g3 + %g5], %g5	! We have a pointer to the handler
+1:
+	brnz,pt	%g5, setup_sparcintr	! branch if valid handle
+	 nop
+
+	ba,a	3b			! log if invalid handle
+	 nop
+2:
+	sir				! out of bounds - crash
 /*
  * Ultra1 and Ultra2 CPUs use soft interrupts for everything.  What we do
  * on a soft interrupt, is we should check which bits in SOFTINT(%asr22)
@@ -3910,6 +3951,12 @@
 	stx	%g0, [%l1]		! Clear intr source
 	membar	#Sync			! Should not be needed
 0:
+	ldx	[%l2 + IH_ACK], %l1	! ih->ih_ack
+	brz,pn	%l1, 1f
+	 nop
+	jmpl	%l1, %o7		! (*ih->ih_ack)(ih)
+	 mov	%l2, %o0
+1:	
 	cmp	%l7, -1
 	bne,pn	CCCR, 2b		! 'Nother?
 	 mov	%l7, %l2