Index: sys/arch/sparc64/include/ctlreg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/include/ctlreg.h,v
retrieving revision 1.62
diff -u -r1.62 ctlreg.h
--- sys/arch/sparc64/include/ctlreg.h	1 Apr 2015 18:38:30 -0000	1.62
+++ sys/arch/sparc64/include/ctlreg.h	2 Feb 2016 20:54:20 -0000
@@ -55,7 +55,7 @@
 #define	ASI_PHYS_CACHED_LITTLE		0x1c	/* [4u] MMU bypass to main memory, little endian */
 #define	ASI_PHYS_NON_CACHED_LITTLE	0x1d	/* [4u] MMU bypass to I/O location, little endian */
 
-#define ASI_MMU				0x21	/* [4v] MMU context control - both IMMU and DMMU */
+#define ASI_MMU_CONTEXTID		0x21	/* [4v] MMU context control - both IMMU and DMMU */
 
 #define	ASI_NUCLEUS_QUAD_LDD		0x24	/* [4u] use w/LDDA to load 128-bit item */
 #define	ASI_QUEUE			0x25	/* [4v] interrupt queue registers */
@@ -864,16 +864,6 @@
 SPARC64_ST_DEF64(stxa, uint64_t)
 
 
-/* set dmmu secondary context */
-static __inline void
-dmmu_set_secondary_context(uint ctx)
-{
-	__asm volatile(
-		"stxa %0,[%1]%2;	"
-		"membar #Sync		"
-		: : "r" (ctx), "r" (CTX_SECONDARY), "n" (ASI_DMMU)
-		: "memory");
-}
 
 /* flush address from data cache */
 #define	flush(loc) __asm volatile("flush %0" : : "r" ((__uintptr_t)(loc)))
Index: sys/arch/sparc64/sparc64/locore.s
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/locore.s,v
retrieving revision 1.386
diff -u -r1.386 locore.s
--- sys/arch/sparc64/sparc64/locore.s	6 Nov 2015 15:30:59 -0000	1.386
+++ sys/arch/sparc64/sparc64/locore.s	2 Feb 2016 20:54:20 -0000
@@ -129,7 +129,7 @@
 	
 #ifdef SUN4V
 	.macro	SET_MMU_CONTEXTID_SUN4V ctxid,ctx
-	stxa	\ctxid, [\ctx] ASI_MMU;
+	stxa	\ctxid, [\ctx] ASI_MMU_CONTEXTID;
 	.endm
 #endif	
 		
Index: sys/arch/sparc64/sparc64/pmap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/pmap.c,v
retrieving revision 1.300
diff -u -r1.300 pmap.c
--- sys/arch/sparc64/sparc64/pmap.c	27 Nov 2015 13:51:24 -0000	1.300
+++ sys/arch/sparc64/sparc64/pmap.c	2 Feb 2016 20:54:20 -0000
@@ -158,6 +158,25 @@
 
 static void ctx_free(struct pmap *, struct cpu_info *);
 
+/* set dmmu secondary context */
+static __inline void
+dmmu_set_secondary_context(uint ctx)
+{
+	if (!CPU_ISSUN4V)
+		__asm volatile(
+			"stxa %0,[%1]%2;	"
+			"membar #Sync		"
+			: : "r" (ctx), "r" (CTX_SECONDARY), "n" (ASI_DMMU)
+			: "memory");
+	else
+		__asm volatile(
+			"stxa %0,[%1]%2;	"
+			"membar #Sync		"
+			: : "r" (ctx), "r" (CTX_SECONDARY), "n" (ASI_MMU_CONTEXTID)
+			: "memory");
+		
+}
+
 /*
  * Check if any MMU has a non-zero context
  */