Index: sys/arch/sparc64/sparc64/cache.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/cache.c,v
retrieving revision 1.9
diff -u -r1.9 cache.c
--- sys/arch/sparc64/sparc64/cache.c	30 Dec 2014 18:29:20 -0000	1.9
+++ sys/arch/sparc64/sparc64/cache.c	4 Jan 2015 19:27:51 -0000
@@ -78,6 +78,8 @@
 void	(*sp_tlb_flush_pte)(vaddr_t, int)	= sp_tlb_flush_pte_us;
 void	(*sp_tlb_flush_all)(void)		= sp_tlb_flush_all_us;
 
+void	(*cache_flush_phys)(paddr_t, psize_t, int) = cache_flush_phys_us;
+
 static void
 sp_tlb_flush_pte_sun4v(vaddr_t va, int ctx)
 {
@@ -93,6 +95,13 @@
 	panic("sp_tlb_flush_all_sun4v() not implemented yet");
 }
 
+
+static void
+cache_flush_phys_sun4v(paddr_t pa, psize_t size, int ecache)
+{
+	panic("cache_flush_phys_sun4v() not implemented yet");
+}
+
 void
 cache_setup_funcs(void)
 {
@@ -122,14 +131,16 @@
 #endif
 	}
 
-	/* Prepare sp_tlb_flush_* functions */
+	/* Prepare sp_tlb_flush_* and cache_flush_phys() functions */
 	if (CPU_ISSUN4V) {
 		sp_tlb_flush_pte = sp_tlb_flush_pte_sun4v;
 		sp_tlb_flush_all = sp_tlb_flush_all_sun4v;
+		cache_flush_phys = cache_flush_phys_sun4v; 
 	} else {
 		if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP()) {
 			sp_tlb_flush_pte = sp_tlb_flush_pte_usiii;
 			sp_tlb_flush_all = sp_tlb_flush_all_usiii;
+			cache_flush_phys = cache_flush_phys_usiii;
 		}
 	}
 
Index: sys/arch/sparc64/sparc64/cache.h
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/cache.h,v
retrieving revision 1.27
diff -u -r1.27 cache.h
--- sys/arch/sparc64/sparc64/cache.h	30 Dec 2014 18:29:20 -0000	1.27
+++ sys/arch/sparc64/sparc64/cache.h	4 Jan 2015 19:27:51 -0000
@@ -101,15 +101,7 @@
 /* The following flush a range from the D$ and I$ but not E$. */
 void	cache_flush_phys_us(paddr_t, psize_t, int);
 void	cache_flush_phys_usiii(paddr_t, psize_t, int);
-
-static __inline__ void
-cache_flush_phys(paddr_t pa, psize_t size, int ecache)
-{
-	if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP())
-		cache_flush_phys_usiii(pa, size, ecache);
-	else
-		cache_flush_phys_us(pa, size, ecache);
-}
+extern void (*cache_flush_phys)(paddr_t, psize_t, int);
 
 /* SPARC64 specific */
 /* Assembly routines to flush TLB mappings */