Index: conf/GENERIC
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/conf/GENERIC,v
retrieving revision 1.136
diff -p -r1.136 GENERIC
*** conf/GENERIC	4 Apr 2011 10:25:08 -0000	1.136
--- conf/GENERIC	26 Apr 2011 09:37:55 -0000
*************** maxusers	64
*** 30,36 ****
  
  
  # Options for variants of the Sun SPARC architecure.
- # We currently support three architecture types; at least one is required.
  options 	SUN4U		# sun4u - UltraSPARC
  #options 	BLINK		# blink the system LED
  
--- 30,35 ----
Index: include/param.h
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/include/param.h,v
retrieving revision 1.44
diff -p -r1.44 param.h
*** include/param.h	8 Feb 2010 19:02:32 -0000	1.44
--- include/param.h	26 Apr 2011 09:37:55 -0000
*************** extern void	delay(unsigned int);
*** 230,235 ****
--- 230,239 ----
  
  extern int cputyp;
  
+ #define CPU_ISSUN4U     (cputyp == CPU_SUN4U)
+ #define CPU_ISSUN4US    (cputyp == CPU_SUN4US)
+ #define CPU_ISSUN4V     (cputyp == CPU_SUN4V)
+ 
  #endif /* _LOCORE */
  #endif /* _KERNEL */
  
*************** extern int cputyp;
*** 240,245 ****
--- 244,251 ----
  #define CPU_SUN4C	1
  #define CPU_SUN4M	2
  #define CPU_SUN4U	3
+ #define CPU_SUN4US	4
+ #define CPU_SUN4V	5
  
  /*
   * Shorthand CPU-type macros. Enumerate all eight cases.
*************** extern int cputyp;
*** 255,261 ****
   * extra memory references they'll generate.
   */
  
- #define CPU_ISSUN4U	(1)
  #define CPU_ISSUN4M	(0)
  #define CPU_ISSUN4C	(0)
  #define CPU_ISSUN4	(0)
--- 261,266 ----
Index: sparc64/autoconf.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/autoconf.c,v
retrieving revision 1.176
diff -p -r1.176 autoconf.c
*** sparc64/autoconf.c	11 Aug 2010 19:14:26 -0000	1.176
--- sparc64/autoconf.c	26 Apr 2011 09:37:55 -0000
*************** void *bootinfo = 0;
*** 137,142 ****
--- 137,145 ----
  int kgdb_break_at_attach;
  #endif
  
+ /* Default to sun4u */
+ int cputyp = CPU_SUN4U;
+ 
  #define	OFPATHLEN	128
  #define	OFNODEKEY	"OFpnode"
  
*************** bootstrap(void *o0, void *bootargs, void
*** 254,259 ****
--- 257,263 ----
  {
  	void *bi;
  	long bmagic;
+ 	char buf[32];
  
  #if NKSYMS || defined(DDB) || defined(MODULAR)
  	struct btinfo_symtab *bi_sym;
*************** die_old_boot_loader:
*** 329,334 ****
--- 333,345 ----
  #endif
  #endif
  
+ 	if (OF_getprop(findroot(), "compatible", buf, sizeof(buf)) > 0) {
+ 		if (strcmp(buf, "sun4us") == 0)
+ 			cputyp = CPU_SUN4US;
+ 		else if (strcmp(buf, "sun4v") == 0)
+ 			cputyp = CPU_SUN4V;
+ 	}
+ 
  	LOOKUP_BOOTINFO(bi_count, BTINFO_DTLB_SLOTS);
  	kernel_tlb_slots = bi_count->count;
  	LOOKUP_BOOTINFO(bi_tlb, BTINFO_DTLB);
Index: sparc64/cache.h
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/cache.h,v
retrieving revision 1.18
diff -p -r1.18 cache.h
*** sparc64/cache.h	28 Mar 2010 05:24:00 -0000	1.18
--- sparc64/cache.h	26 Apr 2011 09:37:55 -0000
*************** void	cache_flush_phys_usiii(paddr_t, psi
*** 93,98 ****
--- 93,100 ----
  static __inline__ void
  dcache_flush_page(paddr_t pa)
  {
+ 	if (CPU_ISSUN4US || CPU_ISSUN4V)
+ 		return;
  	if (CPU_IS_USIII_UP())
  		dcache_flush_page_usiii(pa);
  	else
Index: sparc64/clock.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/clock.c,v
retrieving revision 1.102
diff -p -r1.102 clock.c
*** sparc64/clock.c	12 Mar 2011 11:42:57 -0000	1.102
--- sparc64/clock.c	26 Apr 2011 09:37:55 -0000
*************** timerattach(struct device *parent, struc
*** 234,240 ****
  	     (CPU_UPAID << INTMAP_TID_SHIFT));
  
  	/* Install the appropriate interrupt vector here */
! 	level10.ih_number = ma->ma_interrupts[0];
  	level10.ih_clr = &timerreg_4u.t_clrintr[0];
  	intr_establish(PIL_CLOCK, true, &level10);
  	printf(" irq vectors %lx", (u_long)level10.ih_number);
--- 234,240 ----
  	     (CPU_UPAID << INTMAP_TID_SHIFT));
  
  	/* Install the appropriate interrupt vector here */
! 	level10.ih_number = INTVEC(ma->ma_interrupts[0]);
  	level10.ih_clr = &timerreg_4u.t_clrintr[0];
  	intr_establish(PIL_CLOCK, true, &level10);
  	printf(" irq vectors %lx", (u_long)level10.ih_number);
*************** timerattach(struct device *parent, struc
*** 242,248 ****
  	/*
  	 * On SMP kernel, don't establish interrupt to use it as timecounter.
  	 */
! 	level14.ih_number = ma->ma_interrupts[1];
  	level14.ih_clr = &timerreg_4u.t_clrintr[1];
  	intr_establish(PIL_STATCLOCK, true, &level14);
  	printf(" and %lx", (u_long)level14.ih_number);
--- 242,248 ----
  	/*
  	 * On SMP kernel, don't establish interrupt to use it as timecounter.
  	 */
! 	level14.ih_number = INTVEC(ma->ma_interrupts[1]);
  	level14.ih_clr = &timerreg_4u.t_clrintr[1];
  	intr_establish(PIL_STATCLOCK, true, &level14);
  	printf(" and %lx", (u_long)level14.ih_number);
Index: sparc64/locore.s
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/locore.s,v
retrieving revision 1.332
diff -p -r1.332 locore.s
*** sparc64/locore.s	20 Dec 2010 00:25:44 -0000	1.332
--- sparc64/locore.s	26 Apr 2011 09:37:55 -0000
*************** interrupt_vector:
*** 3086,3093 ****
  	 sethi	%hi(KERNBASE), %g1
  
  	cmp	%g7, %g1
! 	bl,pt	%xcc, Lsoftint_regular	! >= KERNBASE is a fast cross-call
! 	 cmp	%g7, MAXINTNUM
  
  	mov	IRDR_1H, %g2
  	ldxa	[%g2] ASI_IRDR, %g2	! Get IPI handler argument 1
--- 3086,3093 ----
  	 sethi	%hi(KERNBASE), %g1
  
  	cmp	%g7, %g1
! 	bl,a,pt	%xcc, Lsoftint_regular	! >= KERNBASE is a fast cross-call
! 	 and	%g7, (MAXINTNUM-1), %g7	! XXX make sun4us work
  
  	mov	IRDR_1H, %g2
  	ldxa	[%g2] ASI_IRDR, %g2	! Get IPI handler argument 1
*************** interrupt_vector:
*** 3100,3106 ****
  	jmpl	%g7, %g0
  	 nop
  #else
! 	 cmp	%g7, MAXINTNUM
  #endif
  
  Lsoftint_regular:
--- 3100,3106 ----
  	jmpl	%g7, %g0
  	 nop
  #else
! 	and	%g7, (MAXINTNUM-1), %g7	! XXX make sun4us work
  #endif
  
  Lsoftint_regular:
*************** Lsoftint_regular:
*** 3108,3115 ****
  	membar	#Sync			! Should not be needed due to retry
  	sllx	%g7, PTRSHFT, %g5	! Calculate entry number
  	sethi	%hi(_C_LABEL(intrlev)), %g3
! 	bgeu,pn	%xcc, 3f
! 	 or	%g3, %lo(_C_LABEL(intrlev)), %g3
  	LDPTR	[%g3 + %g5], %g5	! We have a pointer to the handler
  	brz,pn	%g5, 3f			! NULL means it isn't registered yet.  Skip it.
  	 nop
--- 3108,3114 ----
  	membar	#Sync			! Should not be needed due to retry
  	sllx	%g7, PTRSHFT, %g5	! Calculate entry number
  	sethi	%hi(_C_LABEL(intrlev)), %g3
! 	or	%g3, %lo(_C_LABEL(intrlev)), %g3
  	LDPTR	[%g3 + %g5], %g5	! We have a pointer to the handler
  	brz,pn	%g5, 3f			! NULL means it isn't registered yet.  Skip it.
  	 nop
Index: sparc64/pmap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/pmap.c,v
retrieving revision 1.270
diff -p -r1.270 pmap.c
*** sparc64/pmap.c	24 Feb 2011 08:42:30 -0000	1.270
--- sparc64/pmap.c	26 Apr 2011 09:37:55 -0000
*************** pmap_dumpmmu(int (*dump)(dev_t, daddr_t,
*** 2334,2340 ****
  
  	/* Fill in MD segment header (interpreted by MD part of libkvm) */
  	kcpu = (cpu_kcore_hdr_t *)((long)bp + ALIGN(sizeof(kcore_seg_t)));
! 	kcpu->cputype = CPU_SUN4U;
  	kcpu->kernbase = (uint64_t)KERNBASE;
  	kcpu->cpubase = (uint64_t)CPUINFO_VA;
  
--- 2334,2340 ----
  
  	/* Fill in MD segment header (interpreted by MD part of libkvm) */
  	kcpu = (cpu_kcore_hdr_t *)((long)bp + ALIGN(sizeof(kcore_seg_t)));
! 	kcpu->cputype = cputyp;
  	kcpu->kernbase = (uint64_t)KERNBASE;
  	kcpu->cpubase = (uint64_t)CPUINFO_VA;
  
*************** pmap_page_cache(struct pmap *pm, paddr_t
*** 3346,3351 ****
--- 3346,3359 ----
  	vaddr_t va;
  	int rv;
  
+ #if 0
+ 	/*
+ 	 * Why is this?
+ 	 */
+ 	if (CPU_ISSUN4US || CPU_ISSUN4V)
+ 		return;
+ #endif
+ 
  	KASSERT(mutex_owned(&pmap_lock));
  
  	DPRINTF(PDB_ENTER, ("pmap_page_uncache(%llx)\n",