? aarch64/aarch64/locore-seattle.patch
? arm/dts/styx-overdrive1000.dts
? arm/fdt/gic_fdt.c.irqhack.diff
Index: aarch64/aarch64/locore.S
===================================================================
RCS file: /cvsroot/src/sys/arch/aarch64/aarch64/locore.S,v
retrieving revision 1.25
diff -p -u -u -r1.25 locore.S
--- aarch64/aarch64/locore.S	10 Sep 2018 11:05:12 -0000	1.25
+++ aarch64/aarch64/locore.S	14 Sep 2018 12:01:30 -0000
@@ -177,7 +177,8 @@ ENTRY_NP(aarch64_start)
 
 	bl	init_sysregs
 
-	bl	arm_boot_l0pt_init
+	bl	arm_boot_l0pt_init_new
+//	bl	arm_boot_l0pt_init
 
 	VERBOSE("MMU Enable...")
 	bl	mmu_enable
@@ -602,6 +603,16 @@ ENTRY_NP(print_x2)
 END(print_x2)
 
 ENTRY_NP(arm_boot_l0pt_init)
+	ADDR	x0, ttbr0_l0table
+	ADDR	x1, ttbr0_save
+	str	x0, [x1]
+	msr	ttbr0_el1, x0
+
+	ADDR	x0, ttbr1_l0table
+	ADDR	x1, ttbr1_save
+	str	x0, [x1]
+	msr	ttbr1_el1, x0
+
 	stp	x0, lr, [sp, #-16]!
 
 	/* Clean the page table */
@@ -911,6 +922,125 @@ ENTRY_NP(l2_setblocks)
 	ret
 END(l2_setblocks)
 
+
+//#define EL1_PHYSMEM_START	0x0000000000000000
+#define EL1_PHYSMEM_START	0x0000008000000000
+#define EL1_PHYSMEM_SIZE	(1024 * 1024 * 1024 * 16)	/* 16Gbyte */
+
+ENTRY_NP(arm_boot_l0pt_init_new)
+	stp	x0, lr, [sp, #-16]!
+
+	bl	bootpagetable_alloc
+	ADDR	x1, ttbr0_save
+	str	x0, [x1]
+	msr	ttbr0_el1, x0
+
+	bl	bootpagetable_alloc
+	ADDR	x1, ttbr1_save
+	str	x0, [x1]
+	msr	ttbr1_el1, x0
+
+	VERBOSE("Creating VA=PA tables (0x00000000-0xffffffff)\r\n")
+	mov	x5, xzr					/* noblock = 0 */
+	adr	x4, bootpagetable_alloc			/* allocator */
+	mov	x3, #L2_BLKPAG_ATTR_DEVICE_MEM		/* attr */
+	mov	x2, #(1024*1024*1024*4)			/* size */
+	mov	x1, xzr					/* pa */
+	mov	x0, xzr					/* va */
+	/* bootpagetable_enter(vaddr_t va, paddr_t pa, psize_t size, pt_entry_t attr, pd_entry_t *(*physpage_allocator)(void), bool noblock); */
+	bl	bootpagetable_enter
+
+	VERBOSE("Creating VA=PA tables for main memory\r\n")
+	mov	x5, xzr					/* noblock = 0 */
+	adr	x4, bootpagetable_alloc			/* allocator */
+	mov	x3, #L2_BLKPAG_ATTR_DEVICE_MEM		/* attr */
+	mov	x2, #EL1_PHYSMEM_SIZE			/* size */
+	ldr	x1, =EL1_PHYSMEM_START			/* pa */
+	bic	x1, x1, #(L1_SIZE - 1)
+	ldr	x0, =EL1_PHYSMEM_START			/* va */
+	bic	x0, x0, #(L1_SIZE - 1)
+	/* bootpagetable_enter(vaddr_t va, paddr_t pa, psize_t size, pt_entry_t attr, pd_entry_t *(*physpage_allocator)(void), bool noblock); */
+	bl	bootpagetable_enter
+
+	VERBOSE("Creating KSEG tables for 0x00000000-0xffffffff\r\n")
+	mov	x5, xzr					/* noblock = 0 */
+	adr	x4, bootpagetable_alloc			/* allocator */
+	mov	x3, #L2_BLKPAG_ATTR_NORMAL_WB
+	orr	x3, x3, #(LX_BLKPAG_PXN|LX_BLKPAG_UXN)	/* attr */
+	mov	x2, #(1024*1024*1024*4)			/* size */
+	mov	x1, xzr					/* pa */
+	mov	x0, #AARCH64_KSEG_START			/* va */
+	bl	bootpagetable_enter
+
+	VERBOSE("Creating KSEG tables for main memory\r\n")
+	mov	x5, xzr					/* noblock = 0 */
+	adr	x4, bootpagetable_alloc			/* allocator */
+	mov	x3, #L2_BLKPAG_ATTR_NORMAL_WB
+	orr	x3, x3, #(LX_BLKPAG_PXN|LX_BLKPAG_UXN)	/* attr */
+	mov	x2, #EL1_PHYSMEM_SIZE			/* size */
+	ldr	x1, =EL1_PHYSMEM_START			/* pa */
+	mov	x0, #AARCH64_KSEG_START
+#if EL1_PHYSMEM_START != 0
+	orr	x0, x0, #EL1_PHYSMEM_START		/* va */
+#endif
+	bl	bootpagetable_enter
+
+	VERBOSE("Creating KVA=PA tables\r\n")
+	mov	x5, xzr					/* noblock = 0 */
+	adr	x4, bootpagetable_alloc			/* allocator */
+	mov	x3, #(L2_BLKPAG_ATTR_NORMAL_WB|LX_BLKPAG_UXN)	/* attr */
+
+	/* kernelsize = _end - start */
+	ldr	x1, =start
+	ldr	x2, =_end
+	sub	x2, x2, x1
+	/* round up kernelsize to L2_SIZE (2MB) */
+	add	x2, x2, #L2_SIZE
+	sub	x2, x2, #1
+	bic	x2, x2, #(L2_SIZE - 1)
+
+	adr	x1, start				/* pa */
+	bic	x1, x1, #(L2_SIZE - 1)
+
+	mov	x0, #VM_MIN_KERNEL_ADDRESS		/* va */
+	bl	bootpagetable_enter
+
+	VERBOSE("Creating devmap tables\r\n")
+	mov	x5, #1					/* noblock = 1 */
+	adr	x4, bootpagetable_alloc			/* allocator */
+	mov	x3, xzr					/* attr (unused) */
+	mov	x2, #(254*1024*1024)			/* size */
+	mov	x1, xzr					/* pa (unused) */
+	ldr	x0, .L_devmap_addr			/* va */
+	bl	bootpagetable_enter
+
+	VERBOSE("OK\r\n");
+	ldp	x0, lr, [sp], #16
+	ret
+END(arm_boot_l0pt_init_new)
+
+#define BOOTPAGETABLENUM	512
+
+ENTRY_NP(bootpagetable_alloc)
+	ADDR	x1, boot_pagetables_used
+	ldr	x0, [x1]
+	cmp	x0, #BOOTPAGETABLENUM
+	bcs	bootpagetable_alloc_err
+	add	x2, x0, #1
+	str	x2, [x1]
+	lsl	x0, x0, #PGSHIFT
+	ADDR	x1, boot_pagetables
+	add	x0, x0, x1
+	ret
+bootpagetable_alloc_err:
+	PRINT("increase BOOTPAGETABLENUML\r\n")
+1:	wfi
+	b	1b
+END(bootpagetable_alloc)
+
+
+
+
 ENTRY_NP(init_sysregs)
 	stp	x0, lr, [sp, #-16]!
 
@@ -946,10 +1076,11 @@ END(mmu_disable)
 
 ENTRY_NP(mmu_enable)
 	dsb	sy
-
-	ADDR	x0, ttbr0_l0table
+	ADDR	x0, ttbr0_save
+	ldr	x0, [x0]
 	msr	ttbr0_el1, x0
-	ADDR	x0, ttbr1_l0table
+	ADDR	x0, ttbr1_save
+	ldr	x0, [x0]
 	msr	ttbr1_el1, x0
 	isb
 
@@ -1075,6 +1206,14 @@ sctlr_clear:
 	    SCTLR_A |       /* Alignment check enable */ \
 	    0)
 
+	.data
+	.align 3
+boot_pagetables_used:
+	.quad	0
+ttbr0_save:
+	.quad	0
+ttbr1_save:
+	.quad	0
 
 	.bss
 
@@ -1116,3 +1255,7 @@ ttbr1_l2table_kva:
 ttbr1_l2table_devmap:
 	.space	PAGE_SIZE
 mmutables_end:
+
+
+boot_pagetables:
+	.space	PAGE_SIZE * BOOTPAGETABLENUM
Index: aarch64/aarch64/pmap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/aarch64/aarch64/pmap.c,v
retrieving revision 1.23
diff -p -u -u -r1.23 pmap.c
--- aarch64/aarch64/pmap.c	10 Sep 2018 16:43:24 -0000	1.23
+++ aarch64/aarch64/pmap.c	14 Sep 2018 12:01:30 -0000
@@ -330,6 +330,8 @@ pmap_devmap_register(const struct pmap_d
 	pmap_devmap_table = table;
 }
 
+void	db_printf(const char *, ...) __printflike(1, 2);
+
 void
 pmap_devmap_bootstrap(const struct pmap_devmap *table)
 {
@@ -339,6 +341,11 @@ pmap_devmap_bootstrap(const struct pmap_
 
 	pmap_devmap_register(table);
 
+	VPRINTF("%s: ttbr0=0x%lx, ttbr1=0x%lx\n", __func__, reg_ttbr0_el1_read(), reg_ttbr1_el1_read());
+
+	//pmap_db_pteinfo(0xfffffffff0000000, db_printf);
+	pmap_db_pteinfo(0xfffffffff0000000, printf);
+
 	l0 = (void *)AARCH64_PA_TO_KVA(reg_ttbr1_el1_read());
 
 	VPRINTF("%s:\n", __func__);
@@ -383,6 +390,7 @@ pmap_devmap_bootstrap(const struct pmap_
 		    table[i].pd_prot,
 		    table[i].pd_flags);
 	}
+	VPRINTF("%s: done\n", __func__);
 }
 
 const struct pmap_devmap *
@@ -1132,6 +1140,7 @@ _pmap_protect_pv(struct vm_page *pg, str
 		pteprot |= VM_PROT_WRITE;
 	if (l3pte_executable(pte, user))
 		pteprot |= VM_PROT_EXECUTE;
+cpu_icache_sync_range(pv->pv_va, PAGE_SIZE);
 
 	/* new prot = prot & pteprot & mdattr */
 	pte = _pmap_pte_adjust_prot(pte, prot & pteprot, mdattr, user);
@@ -1220,8 +1229,8 @@ pmap_protect(struct pmap *pm, vaddr_t sv
 			UVMHIST_LOG(pmaphist, "icache_sync: "
 			    "pm=%p, va=%016lx, pte: %016lx -> %016lx",
 			    pm, va, opte, pte);
+			PTE_ICACHE_SYNC_PAGE(pte, ptep, pm, va, true);
 			if (!l3pte_writable(pte)) {
-				PTE_ICACHE_SYNC_PAGE(pte, ptep, pm, va, true);
 				atomic_swap_64(ptep, pte);
 				AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true);
 			} else {
@@ -1247,6 +1256,7 @@ pmap_activate(struct lwp *l)
 	UVMHIST_FUNC(__func__);
 	UVMHIST_CALLED(pmaphist);
 
+aarch64_icache_inv_all();
 	if (pm == pmap_kernel())
 		return;
 	if (l != curlwp)
@@ -1554,8 +1564,8 @@ _pmap_enter(struct pmap *pm, vaddr_t va,
 		UVMHIST_LOG(pmaphist,
 		    "icache_sync: pm=%p, va=%016lx, pte: %016lx -> %016lx",
 		    pm, va, opte, pte);
+		PTE_ICACHE_SYNC_PAGE(pte, ptep, pm, va, l3only);
 		if (!l3pte_writable(pte)) {
-			PTE_ICACHE_SYNC_PAGE(pte, ptep, pm, va, l3only);
 			atomic_swap_64(ptep, pte);
 			AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va ,true);
 		} else {
@@ -2212,7 +2222,8 @@ pmap_db_pteinfo(vaddr_t va, void (*pr)(c
 	 * traverse L0 -> L1 -> L2 -> L3 table
 	 */
 
-	l0 = pm->pm_l0table;
+//	l0 = pm->pm_l0table;
+	l0 = (void *)reg_ttbr1_el1_read();
 
 	pr("TTBR%d=%016llx (%016llx)", user ? 0 : 1,
 	    pm->pm_l0table_pa, l0);
@@ -2271,3 +2282,110 @@ pmap_db_pteinfo(vaddr_t va, void (*pr)(c
 	}
 }
 #endif /* DDB */
+
+/*
+ * XXX: this function will be called from locore without MMU.
+ * cannot refer bss/data section, and must be position independent.
+ */
+void bootpagetable_enter(vaddr_t, paddr_t, psize_t, pt_entry_t, pd_entry_t *(*)(void), bool);
+
+void
+bootpagetable_enter(vaddr_t va, paddr_t pa, psize_t size, pt_entry_t attr, pd_entry_t *(*physpage_allocator)(void), bool noblock)
+{
+	int level, idx;
+	vaddr_t va_end;
+	pd_entry_t *l0, *l1, *l2, *l3, pte;
+
+	/* select block size and level needed */
+	vaddr_t addr = va | pa | size;
+	if ((addr & (L2_SIZE - 1)) != 0)
+		level = 3;
+	else if ((addr & (L1_SIZE - 1)) != 0)
+		level = 2;
+	else
+		level = 1;
+
+	va_end = va + size;
+
+	while (va < va_end) {
+		/*
+		 * 0x0000xxxxxxxxxxxx -> ttbr0
+		 * 0xffffxxxxxxxxxxxx -> ttbr1
+		 */
+		l0 = (pd_entry_t *)((va & 0x8000000000000000UL) ? reg_ttbr1_el1_read() : reg_ttbr0_el1_read());
+
+		idx = (va & L0_ADDR_BITS) >> L0_SHIFT;
+		if (l0[idx] == 0) {
+			l1 = physpage_allocator();
+			pte = (uint64_t)l1 | L0_TABLE;
+			l0[idx] = pte;
+		} else {
+			l1 = (uint64_t *)(l0[idx] & LX_TBL_PA);
+		}
+
+		idx = (va & L1_ADDR_BITS) >> L1_SHIFT;
+		if (level == 1) {
+			if (!noblock) {
+				pte = pa | L1_BLOCK | LX_BLKPAG_AF | LX_BLKPAG_AP_RW | attr;
+#ifdef MULTIPROCESSOR
+				pte |= LX_BLKPAG_SH_IS;
+#endif
+				l1[idx] = pte;
+			}
+			goto nextblk;
+		}
+
+		if (l1[idx] == 0) {
+			l2 = physpage_allocator();
+			pte = (uint64_t)l2 | L1_TABLE;
+			l1[idx] = pte;
+		} else {
+			l2 = (uint64_t *)(l1[idx] & LX_TBL_PA);
+		}
+
+		idx = (va & L2_ADDR_BITS) >> L2_SHIFT;
+		if (level == 2) {
+			if (!noblock) {
+				pte = pa | L2_BLOCK | LX_BLKPAG_AF | LX_BLKPAG_AP_RW | attr;
+#ifdef MULTIPROCESSOR
+				pte |= LX_BLKPAG_SH_IS;
+#endif
+				l2[idx] = pte;
+			}
+			goto nextblk;
+		}
+
+		if (l2[idx] == 0) {
+			l3 = physpage_allocator();
+			pte = (uint64_t)l3 | L2_TABLE;
+			l2[idx] = pte;
+		} else {
+			l3 = (uint64_t *)(l2[idx] & LX_TBL_PA);
+		}
+
+		if (!noblock) {
+			idx = (va & L3_ADDR_BITS) >> L3_SHIFT;
+			pte = pa | L3_PAGE | LX_BLKPAG_AF | LX_BLKPAG_AP_RW | attr;
+#ifdef MULTIPROCESSOR
+			pte |= LX_BLKPAG_SH_IS;
+#endif
+			l3[idx] = pte;
+		}
+
+ nextblk:
+		switch (level) {
+		case 1:
+			va += L1_SIZE;
+			pa += L1_SIZE;
+			break;
+		case 2:
+			va += L2_SIZE;
+			pa += L2_SIZE;
+			break;
+		case 3:
+			va += L3_SIZE;
+			pa += L3_SIZE;
+			break;
+		}
+	}
+}
Index: aarch64/aarch64/sig_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/aarch64/aarch64/sig_machdep.c,v
retrieving revision 1.3
diff -p -u -u -r1.3 sig_machdep.c
--- aarch64/aarch64/sig_machdep.c	17 Jul 2018 00:36:30 -0000	1.3
+++ aarch64/aarch64/sig_machdep.c	14 Sep 2018 12:01:30 -0000
@@ -89,7 +89,7 @@ sendsig_siginfo(const ksiginfo_t *ksi, c
 		/*
 		 * Thread has trashed its stack.  Blow it away.
 		 */
-		if (error == 0) {
+		if (1 || error == 0) {
 			printf("pid %d.%d(%s): %p(sig %d): bad version %d\n",
 			    p->p_pid, l->l_lid, p->p_comm, __func__,
 			    ksi->ksi_signo, sd->sd_vers);
Index: aarch64/aarch64/trap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/aarch64/aarch64/trap.c,v
retrieving revision 1.9
diff -p -u -u -r1.9 trap.c
--- aarch64/aarch64/trap.c	10 Sep 2018 17:25:15 -0000	1.9
+++ aarch64/aarch64/trap.c	14 Sep 2018 12:01:30 -0000
@@ -75,7 +75,7 @@ __KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.9
 #endif
 
 #ifdef DDB
-int sigill_debug = 0;
+int sigill_debug = 1;
 #endif
 
 const char * const trap_names[] = {
Index: aarch64/include/cpufunc.h
===================================================================
RCS file: /cvsroot/src/sys/arch/aarch64/include/cpufunc.h,v
retrieving revision 1.3
diff -p -u -u -r1.3 cpufunc.h
--- aarch64/include/cpufunc.h	26 Aug 2018 18:15:49 -0000	1.3
+++ aarch64/include/cpufunc.h	14 Sep 2018 12:01:30 -0000
@@ -121,7 +121,8 @@ void aarch64_tlbi_by_asid_va_ll(int, vad
 #define cpu_dcache_inv_range(v,s)	aarch64_dcache_inv_range((v),(s))
 #define cpu_dcache_wb_range(v,s)	aarch64_dcache_wb_range((v),(s))
 #define cpu_idcache_wbinv_range(v,s)	aarch64_idcache_wbinv_range((v),(s))
-#define cpu_icache_sync_range(v,s)	aarch64_icache_sync_range((v),(s))
+//#define cpu_icache_sync_range(v,s)	aarch64_icache_sync_range((v),(s))
+#define cpu_icache_sync_range(v,s)	aarch64_icache_inv_all()
 
 #define cpu_sdcache_wbinv_range(v,p,s)	((void)0)
 #define cpu_sdcache_inv_range(v,p,s)	((void)0)
Index: arm/arm32/bus_dma.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm32/bus_dma.c,v
retrieving revision 1.112
diff -p -u -u -r1.112 bus_dma.c
--- arm/arm32/bus_dma.c	3 Sep 2018 16:29:23 -0000	1.112
+++ arm/arm32/bus_dma.c	14 Sep 2018 12:01:30 -0000
@@ -796,7 +796,7 @@ _bus_dmamap_sync_segment(vaddr_t va, pad
     bool readonly_p)
 {
 
-#ifdef ARM_MMU_EXTENDED
+#if defined(ARM_MMU_EXTENDED) || defined(CPU_CORTEX)
 	/*
 	 * No optimisations are available for readonly mbufs on armv6+, so
 	 * assume it's not readonly from here on.
Index: evbarm/conf/GENERIC64
===================================================================
RCS file: /cvsroot/src/sys/arch/evbarm/conf/GENERIC64,v
retrieving revision 1.35
diff -p -u -u -r1.35 GENERIC64
--- evbarm/conf/GENERIC64	8 Sep 2018 00:42:01 -0000	1.35
+++ evbarm/conf/GENERIC64	14 Sep 2018 12:01:30 -0000
@@ -31,6 +31,8 @@ makeoptions	DTS="
 	rk3399-sapphire-excavator.dts
 	rk3399-sapphire.dts
 
+	styx-overdrive1000.dts
+
 	sun50i-a64-bananapi-m64.dts
 	sun50i-a64-nanopi-a64.dts
 	sun50i-a64-olinuxino.dts