? x86/errata.notes Index: include/specialreg.h =================================================================== RCS file: /cvsroot/src/sys/arch/x86/include/specialreg.h,v retrieving revision 1.56 diff -p -u -r1.56 specialreg.h --- include/specialreg.h 2 Mar 2012 16:41:00 -0000 1.56 +++ include/specialreg.h 27 Mar 2012 21:03:19 -0000 @@ -516,6 +516,9 @@ #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL +#define MSR_DE_CFG 0xc0011029 +#define DE_CFG_ERRATA_721 0x00000001 + /* AMD Family10h MSRs */ #define MSR_OSVW_ID_LENGTH 0xc0010140 #define MSR_OSVW_STATUS 0xc0010141 Index: x86/errata.c =================================================================== RCS file: /cvsroot/src/sys/arch/x86/x86/errata.c,v retrieving revision 1.19 diff -p -u -r1.19 errata.c --- x86/errata.c 23 Jul 2010 22:31:35 -0000 1.19 +++ x86/errata.c 27 Mar 2012 21:03:19 -0000 @@ -1,11 +1,11 @@ /* $NetBSD: errata.c,v 1.19 2010/07/23 22:31:35 cegger Exp $ */ /*- - * Copyright (c) 2007 The NetBSD Foundation, Inc. + * Copyright (c) 2007, 2012 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation - * by Andrew Doran. + * by Andrew Doran and Matthew R. Green. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -41,6 +41,12 @@ * AMD Opteron Processors, Publication #25759, Revision: 3.69, * Issue Date: September 2006 * + * Additional data provided from: Revision Guide for AMD Family 10h + * Processors, Publication #41322, Revision: 3.92, Issue Date: + * March 2012, and, Revision Guide for AMD Family 12h Processors, + * Publication #44739 Revision: 3.10 Issue Date: March 2012, for + * errata 721 only. + * * XXX This should perhaps be integrated with the identcpu code. */ @@ -62,6 +68,7 @@ typedef struct errata { u_short e_reported; u_int e_data1; const uint8_t *e_set; + u_int e_set_mask; bool (*e_act)(struct cpu_info *, struct errata *); uint64_t e_data2; } errata_t; @@ -70,22 +77,58 @@ typedef enum cpurev { BH_E4, CH_CG, CH_D0, DH_CG, DH_D0, DH_E3, DH_E6, JH_E1, JH_E6, SH_B0, SH_B3, SH_C0, SH_CG, SH_D0, SH_E4, SH_E5, DR_BA, DR_B2, DR_B3, + /* some more generic versions applied */ + FAM10, FAM12, OINK } cpurev_t; -static const u_int cpurevs[] = { - BH_E4, 0x0020fb1, CH_CG, 0x0000f82, CH_CG, 0x0000fb2, - CH_D0, 0x0010f80, CH_D0, 0x0010fb0, DH_CG, 0x0000fc0, - DH_CG, 0x0000fe0, DH_CG, 0x0000ff0, DH_D0, 0x0010fc0, - DH_D0, 0x0010ff0, DH_E3, 0x0020fc0, DH_E3, 0x0020ff0, - DH_E6, 0x0020fc2, DH_E6, 0x0020ff2, JH_E1, 0x0020f10, - JH_E6, 0x0020f12, JH_E6, 0x0020f32, SH_B0, 0x0000f40, - SH_B3, 0x0000f51, SH_C0, 0x0000f48, SH_C0, 0x0000f58, - SH_CG, 0x0000f4a, SH_CG, 0x0000f5a, SH_CG, 0x0000f7a, - SH_D0, 0x0010f40, SH_D0, 0x0010f50, SH_D0, 0x0010f70, - SH_E4, 0x0020f51, SH_E4, 0x0020f71, SH_E5, 0x0020f42, - DR_BA, 0x0100f2a, DR_B2, 0x0100f22, DR_B3, 0x0100f23, - OINK +#define SET_ONE_MASK 0xffffffff +#define SET_FAMILY_MASK 0x00ff0000 + +typedef struct cpu_rev_table { + cpurev_t cpu; + u_int cpuid; + u_int mask; +} cpu_rev_table_t; + +static const cpu_rev_table_t cpurevs[] = { + { BH_E4, 0x0020fb1, SET_ONE_MASK }, + { CH_CG, 0x0000f82, SET_ONE_MASK }, + { CH_CG, 0x0000fb2, SET_ONE_MASK }, + { CH_D0, 0x0010f80, SET_ONE_MASK }, + { CH_D0, 0x0010fb0, SET_ONE_MASK }, + { DH_CG, 0x0000fc0, SET_ONE_MASK }, + { DH_CG, 0x0000fe0, SET_ONE_MASK }, + { DH_CG, 0x0000ff0, SET_ONE_MASK }, + { DH_D0, 0x0010fc0, SET_ONE_MASK }, + { DH_D0, 0x0010ff0, SET_ONE_MASK }, + { DH_E3, 0x0020fc0, SET_ONE_MASK }, + { DH_E3, 0x0020ff0, SET_ONE_MASK }, + { DH_E6, 0x0020fc2, SET_ONE_MASK }, + { DH_E6, 0x0020ff2, SET_ONE_MASK }, + { JH_E1, 0x0020f10, SET_ONE_MASK }, + { JH_E6, 0x0020f12, SET_ONE_MASK }, + { JH_E6, 0x0020f32, SET_ONE_MASK }, + { SH_B0, 0x0000f40, SET_ONE_MASK }, + { SH_B3, 0x0000f51, SET_ONE_MASK }, + { SH_C0, 0x0000f48, SET_ONE_MASK }, + { SH_C0, 0x0000f58, SET_ONE_MASK }, + { SH_CG, 0x0000f4a, SET_ONE_MASK }, + { SH_CG, 0x0000f5a, SET_ONE_MASK }, + { SH_CG, 0x0000f7a, SET_ONE_MASK }, + { SH_D0, 0x0010f40, SET_ONE_MASK }, + { SH_D0, 0x0010f50, SET_ONE_MASK }, + { SH_D0, 0x0010f70, SET_ONE_MASK }, + { SH_E4, 0x0020f51, SET_ONE_MASK }, + { SH_E4, 0x0020f71, SET_ONE_MASK }, + { SH_E5, 0x0020f42, SET_ONE_MASK }, + { DR_BA, 0x0100f2a, SET_ONE_MASK }, + { DR_B2, 0x0100f22, SET_ONE_MASK }, + { DR_B3, 0x0100f23, SET_ONE_MASK }, + /* Errata that apply to entire families. */ + { FAM10, 0x0100000, SET_FAMILY_MASK }, + { FAM12, 0x0120000, SET_FAMILY_MASK }, + { OINK, 0, 0 }, }; static const uint8_t x86_errata_set1[] = { @@ -132,6 +175,10 @@ static const uint8_t x86_errata_set10[] DR_BA, DR_B2, DR_B3, OINK }; +static const uint8_t x86_errata_set11[] = { + FAM10, FAM12, OINK +}; + static bool x86_errata_setmsr(struct cpu_info *, errata_t *); static bool x86_errata_testmsr(struct cpu_info *, errata_t *); @@ -141,21 +188,21 @@ static errata_t errata[] = { * and Streaming Stores */ { - 81, FALSE, MSR_DC_CFG, x86_errata_set5, + 81, FALSE, MSR_DC_CFG, x86_errata_set5, SET_ONE_MASK, x86_errata_testmsr, DC_CFG_DIS_SMC_CHK_BUF }, /* * 86: DRAM Data Masking Feature Can Cause ECC Failures */ { - 86, FALSE, MSR_NB_CFG, x86_errata_set1, + 86, FALSE, MSR_NB_CFG, x86_errata_set1, SET_ONE_MASK, x86_errata_testmsr, NB_CFG_DISDATMSK }, /* * 89: Potential Deadlock With Locked Transactions */ { - 89, FALSE, MSR_NB_CFG, x86_errata_set8, + 89, FALSE, MSR_NB_CFG, x86_errata_set8, SET_ONE_MASK, x86_errata_testmsr, NB_CFG_DISIOREQLOCK }, /* @@ -163,7 +210,7 @@ static errata_t errata[] = { * Processor Operation */ { - 94, FALSE, MSR_IC_CFG, x86_errata_set1, + 94, FALSE, MSR_IC_CFG, x86_errata_set1, SET_ONE_MASK, x86_errata_testmsr, IC_CFG_DIS_SEQ_PREFETCH }, /* @@ -175,7 +222,7 @@ static errata_t errata[] = { * can't be applied, it shouldn't be reported. */ { - 97, FALSE, MSR_DC_CFG, x86_errata_set6, + 97, FALSE, MSR_DC_CFG, x86_errata_set6, SET_ONE_MASK, x86_errata_testmsr, DC_CFG_DIS_CNV_WC_SSO }, /* @@ -183,14 +230,14 @@ static errata_t errata[] = { * Failures When Enabled With x8/x16 DRAM Devices */ { - 104, FALSE, MSR_NB_CFG, x86_errata_set7, + 104, FALSE, MSR_NB_CFG, x86_errata_set7, SET_ONE_MASK, x86_errata_testmsr, NB_CFG_DISDATMSK }, /* * 113: Enhanced Write-Combining Feature Causes System Hang */ { - 113, FALSE, MSR_BU_CFG, x86_errata_set3, + 113, FALSE, MSR_BU_CFG, x86_errata_set3, SET_ONE_MASK, x86_errata_setmsr, BU_CFG_WBENHWSBDIS }, /* @@ -198,7 +245,7 @@ static errata_t errata[] = { * Prefetch Mechanism */ { - 69, FALSE, MSR_BU_CFG, x86_errata_set5, + 69, FALSE, MSR_BU_CFG, x86_errata_set5, SET_ONE_MASK, x86_errata_setmsr, BU_CFG_WBPFSMCCHKDIS }, /* @@ -206,7 +253,7 @@ static errata_t errata[] = { * Node-Interleaved Memory */ { - 101, FALSE, 0, x86_errata_set2, + 101, FALSE, 0, x86_errata_set2, SET_ONE_MASK, NULL, 0 }, /* @@ -214,7 +261,7 @@ static errata_t errata[] = { * in an MP System */ { - 106, FALSE, MSR_LS_CFG, x86_errata_set2, + 106, FALSE, MSR_LS_CFG, x86_errata_set2, SET_ONE_MASK, x86_errata_testmsr, LS_CFG_DIS_LS2_SQUISH }, /* @@ -222,7 +269,7 @@ static errata_t errata[] = { * Setting Page Table A/D Bits */ { - 107, FALSE, MSR_BU_CFG, x86_errata_set2, + 107, FALSE, MSR_BU_CFG, x86_errata_set2, SET_ONE_MASK, x86_errata_testmsr, BU_CFG_THRL2IDXCMPDIS }, /* @@ -230,14 +277,14 @@ static errata_t errata[] = { * Multiprocessor Systems */ { - 122, FALSE, MSR_HWCR, x86_errata_set4, + 122, FALSE, MSR_HWCR, x86_errata_set4, SET_ONE_MASK, x86_errata_setmsr, HWCR_FFDIS }, /* * 254: Internal Resource Livelock Involving Cached TLB Reload */ { - 254, FALSE, MSR_BU_CFG, x86_errata_set9, + 254, FALSE, MSR_BU_CFG, x86_errata_set9, SET_ONE_MASK, x86_errata_testmsr, BU_CFG_ERRATA_254 }, /* @@ -245,7 +292,7 @@ static errata_t errata[] = { * Cache Scrub */ { - 261, FALSE, MSR_DC_CFG, x86_errata_set10, + 261, FALSE, MSR_DC_CFG, x86_errata_set10, SET_ONE_MASK, x86_errata_testmsr, DC_CFG_ERRATA_261 }, /* @@ -253,11 +300,11 @@ static errata_t errata[] = { * Accessed or Dirty Bit */ { - 298, FALSE, MSR_HWCR, x86_errata_set9, + 298, FALSE, MSR_HWCR, x86_errata_set9, SET_ONE_MASK, x86_errata_testmsr, HWCR_TLBCACHEDIS }, { - 298, FALSE, MSR_BU_CFG, x86_errata_set9, + 298, FALSE, MSR_BU_CFG, x86_errata_set9, SET_ONE_MASK, x86_errata_testmsr, BU_CFG_ERRATA_298 }, /* @@ -265,9 +312,18 @@ static errata_t errata[] = { * Concurrent L2 and Northbridge Response */ { - 309, FALSE, MSR_BU_CFG, x86_errata_set9, + 309, FALSE, MSR_BU_CFG, x86_errata_set9, SET_ONE_MASK, x86_errata_testmsr, BU_CFG_ERRATA_309 }, +#ifdef __x86_64__ + /* + * 721: Processor May Incorrectly Update Stack Pointer + */ + { + 721, FALSE, MSR_DE_CFG, x86_errata_set11, SET_FAMILY_MASK, + x86_errata_setmsr, DE_CFG_ERRATA_721 + }, +#endif }; static bool @@ -319,10 +375,12 @@ x86_errata(void) x86_cpuid(0x80000001, descs); - for (i = 0;; i += 2) { - if ((rev = cpurevs[i]) == OINK) + for (i = 0;; i++) { + if ((rev = cpurevs[i].cpu) == OINK) { + aprint_verbose_dev(ci->ci_dev, "no errata present"); return; - if (cpurevs[i + 1] == descs[0]) + } + if (cpurevs[1].cpuid == (descs[0] & cpurevs[i].mask)) break; } @@ -332,13 +390,13 @@ x86_errata(void) continue; if (e->e_set != NULL) { for (j = 0; e->e_set[j] != OINK; j++) - if (e->e_set[j] == rev) + if (e->e_set[j] == (rev & e->e_set_mask)) break; if (e->e_set[j] == OINK) continue; } - aprint_debug_dev(ci->ci_dev, "testing for erratum %d\n", + aprint_verbose_dev(ci->ci_dev, "testing for erratum %d\n", e->e_num); if (e->e_act == NULL)