? evbmips/conf/ERLITE.MP
? evbmips/conf/ERLITE.local
Index: mips/cavium/octeon_cpunode.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/cavium/octeon_cpunode.c,v
retrieving revision 1.10
diff -p -u -r1.10 octeon_cpunode.c
--- mips/cavium/octeon_cpunode.c	19 Aug 2016 10:20:42 -0000	1.10
+++ mips/cavium/octeon_cpunode.c	29 Dec 2016 20:20:07 -0000
@@ -189,6 +189,7 @@ octeon_fixup_cpu_info_references(int32_t
 	new_insns[1] &= __BITS(31,16);
 	new_insns[0] |= (uint16_t)((load_addr + 0x8000) >> 16);
 	new_insns[1] |= (uint16_t)load_addr;
+#define DEBUG_VERBOSE
 #ifdef DEBUG_VERBOSE
 	printf("%s: %08x: insn#1 %08x: lui r%u, %d\n",
 	    __func__, load_addr, new_insns[0],
Index: mips/cavium/dev/octeon_gmx.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/cavium/dev/octeon_gmx.c,v
retrieving revision 1.2
diff -p -u -r1.2 octeon_gmx.c
--- mips/cavium/dev/octeon_gmx.c	1 Jun 2015 22:55:12 -0000	1.2
+++ mips/cavium/dev/octeon_gmx.c	29 Dec 2016 20:20:07 -0000
@@ -57,7 +57,16 @@ __KERNEL_RCSID(0, "$NetBSD: octeon_gmx.c
 #include <mips/cavium/dev/octeon_asxvar.h>
 #include <mips/cavium/dev/octeon_gmxvar.h>
 
+#if 1
 #define	dprintf(...)
+#else
+#define dprintf(fmt, ...) do { \
+  struct timeval _tvX; \
+  microtime(&_tvX); \
+  printf("[%lu.%u] %s:%d: " fmt, _tvX.tv_sec, _tvX.tv_usec, \
+	 __func__, __LINE__, ##__VA_ARGS__); \
+} while (0)
+#endif
 #define	OCTEON_ETH_KASSERT	KASSERT
 
 #define	ADDR2UINT64(u, a) \
@@ -917,6 +926,7 @@ octeon_gmx_rgmii_set_mac_addr(struct oct
 }
 
 #define	OCTEON_ETH_USE_GMX_CAM
+#undef	OCTEON_ETH_USE_GMX_CAM
 
 static int
 octeon_gmx_rgmii_set_filter(struct octeon_gmx_port_softc *sc)
@@ -1041,7 +1051,7 @@ setmulti:
 	}
 	/* XXX XXX XXX */
 
-	dprintf("ctl = %llx, cam_en = %llx\n", ctl, cam_en);
+	dprintf("ctl = %"PRIx64", cam_en = %"PRIx64"\n", ctl, cam_en);
 	_GMX_PORT_WR8(sc, GMX0_RX0_ADR_CTL, ctl);
 	_GMX_PORT_WR8(sc, GMX0_RX0_ADR_CAM_EN, cam_en);
 
Index: mips/mips/cpu_subr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/cpu_subr.c,v
retrieving revision 1.30
diff -p -u -r1.30 cpu_subr.c
--- mips/mips/cpu_subr.c	31 Oct 2016 12:49:04 -0000	1.30
+++ mips/mips/cpu_subr.c	29 Dec 2016 20:20:07 -0000
@@ -124,10 +124,11 @@ cpu_info_alloc(struct pmap_tlb_info *ti,
 	KASSERT(cpu_id < MAXCPUS);
 
 #ifdef MIPS64_OCTEON
-	vaddr_t exc_page = MIPS_UTLB_MISS_EXC_VEC + 0x1000*cpu_id;
-	__CTASSERT(sizeof(struct cpu_info) + sizeof(struct pmap_tlb_info) <= 0x1000 - 0x280);
+	KASSERT(cpu_id == 1);
+	vaddr_t exc_page = MIPS_UTLB_MISS_EXC_VEC + PAGE_SIZE*cpu_id;
+	__CTASSERT(sizeof(struct cpu_info) + sizeof(struct pmap_tlb_info) <= PAGE_SIZE - 0x280);
 
-	struct cpu_info * const ci = ((struct cpu_info *)(exc_page + 0x1000)) - 1;
+	struct cpu_info * const ci = ((struct cpu_info *)(exc_page + PAGE_SIZE)) - 1;
 	memset((void *)exc_page, 0, PAGE_SIZE);
 
 	if (ti == NULL) {
Index: mips/mips/mips_fixup.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/mips_fixup.c,v
retrieving revision 1.19
diff -p -u -r1.19 mips_fixup.c
--- mips/mips/mips_fixup.c	8 Oct 2016 08:19:22 -0000	1.19
+++ mips/mips/mips_fixup.c	29 Dec 2016 20:20:07 -0000
@@ -56,6 +56,7 @@ mips_fixup_exceptions(mips_fixup_callbac
 	} else {
 		start = (uint32_t *)(intptr_t)(ebase & ~MIPS_EBASE_CPUNUM);
 	}
+printf("%s: ebase %x mips_cpu_id %x start %p\n", __func__, ebase, mips_options.mips_cpu_id, start);
 #else
 	uint32_t * const start = (uint32_t *)MIPS_KSEG0_START;
 #endif
Index: evbmips/cavium/machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/cavium/machdep.c,v
retrieving revision 1.10
diff -p -u -r1.10 machdep.c
--- evbmips/cavium/machdep.c	28 Dec 2016 03:27:08 -0000	1.10
+++ evbmips/cavium/machdep.c	29 Dec 2016 20:20:07 -0000
@@ -364,8 +364,11 @@ mach_init_memory(u_quad_t memsize)
 
 
 #ifdef MULTIPROCESSOR
-	const u_int cores = mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM;
-	mem_clusters[0].start = cores * 4096;
+	//const u_int cores = mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM;
+	//KASSERTMSG(cores == 2, "cores %d", cores);
+	const u_int cores = 2;
+	mem_clusters[0].start += cores * PAGE_SIZE;
+	mem_clusters[0].size  -= cores * PAGE_SIZE;
 #endif
 
 	/*