Index: sys/dev/ic/dwc_eqos.c
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/dwc_eqos.c,v
retrieving revision 1.1
diff -p -u -r1.1 dwc_eqos.c
--- sys/dev/ic/dwc_eqos.c	3 Jan 2022 17:19:41 -0000	1.1
+++ sys/dev/ic/dwc_eqos.c	5 Jan 2022 00:57:57 -0000
@@ -886,8 +886,30 @@ eqos_intr(void *arg)
 
 	mtl_status = RD4(sc, GMAC_MTL_INTERRUPT_STATUS);
 	if (mtl_status) {
+		uint32_t debug_data = 0, ictrl_status = 0;
+
+		if ((mtl_status & GMAC_MTL_INTERRUPT_STATUS_DBGIS) != 0)
+			debug_data = RD4(sc, GMAC_MTL_FIFO_DEBUG_DATA);
+		if ((mtl_status & GMAC_MTL_INTERRUPT_STATUS_Q0IS) != 0) {
+			uint32_t new_status = 0;
+
+			ictrl_status = RD4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS);
+			if ((ictrl_status & GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS) != 0)
+				new_status |= GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS;
+			if ((ictrl_status & GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS) != 0)
+				new_status |= GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS;
+			if (new_status) {
+				new_status |= (ictrl_status &
+				    (GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE|
+				     GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE));
+				WR4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS, new_status);
+			}
+		}
 		device_printf(sc->sc_dev,
-		    "GMAC_MTL_INTERRUPT_STATUS = 0x%08X\n", mtl_status);
+		    "GMAC_MTL_INTERRUPT_STATUS = 0x%08X, "
+		    "GMAC_MTL_FIFO_DEBUG_DATA = 0x%08X, "
+		    "GMAC_MTL_INTERRUPT_STATUS_Q0IS = 0x%08X\n",
+		    mtl_status, debug_data, ictrl_status);
 	}
 
 	dma_status = RD4(sc, GMAC_DMA_CHAN0_STATUS);
Index: sys/dev/ic/dwc_eqos_reg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/dwc_eqos_reg.h,v
retrieving revision 1.1
diff -p -u -r1.1 dwc_eqos_reg.h
--- sys/dev/ic/dwc_eqos_reg.h	3 Jan 2022 17:19:41 -0000	1.1
+++ sys/dev/ic/dwc_eqos_reg.h	5 Jan 2022 00:57:57 -0000
@@ -164,6 +164,8 @@
 #define	GMAC_MTL_DBG_STS			0x0C0C
 #define	GMAC_MTL_FIFO_DEBUG_DATA		0x0C10
 #define	GMAC_MTL_INTERRUPT_STATUS		0x0C20
+#define	 GMAC_MTL_INTERRUPT_STATUS_DBGIS	(1U << 17)
+#define	 GMAC_MTL_INTERRUPT_STATUS_Q0IS		(1U << 0)
 #define	GMAC_MTL_TXQ0_OPERATION_MODE		0x0D00
 #define	 GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT	2
 #define	 GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK	(0x3U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)