Index: drm/drm_ioctl.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/drm_ioctl.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -p -u -r1.10 -r1.11
--- drm/drm_ioctl.c	28 Aug 2018 03:41:38 -0000	1.10
+++ drm/drm_ioctl.c	14 Sep 2018 05:31:14 -0000	1.11
@@ -703,6 +703,7 @@ drm_ioctl(struct file *fp, unsigned long
 {
 	char stackbuf[128];
 	char *buf = stackbuf;
+	void *data0 = data;
 	struct drm_file *const file = fp->f_data;
 	const unsigned int nr = DRM_IOCTL_NR(cmd);
 	int error;
@@ -761,20 +762,24 @@ drm_ioctl(struct file *fp, unsigned long
 		memcpy(buf, data, IOCPARM_LEN(cmd));
 		memset(buf + IOCPARM_LEN(cmd), 0,
 		    IOCPARM_LEN(ioctl->cmd) - IOCPARM_LEN(cmd));
-		data = buf;
+		data0 = buf;
 	}
 
 	if ((drm_core_check_feature(dev, DRIVER_MODESET) && is_driver_ioctl) ||
 	    ISSET(ioctl->flags, DRM_UNLOCKED)) {
 		/* XXX errno Linux->NetBSD */
-		error = -(*ioctl->func)(dev, data, file);
+		error = -(*ioctl->func)(dev, data0, file);
 	} else {
 		mutex_lock(&drm_global_mutex);
 		/* XXX errno Linux->NetBSD */
-		error = -(*ioctl->func)(dev, data, file);
+		error = -(*ioctl->func)(dev, data0, file);
 		mutex_unlock(&drm_global_mutex);
 	}
 
+	/* If we used a temporary buffer, copy it back out.  */
+	if (data != data0)
+		memcpy(data, data0, IOCPARM_LEN(cmd));
+
 	/* If we had to allocate a heap buffer, free it.  */
 	if (buf != stackbuf)
 		kmem_free(buf, IOCPARM_LEN(ioctl->cmd));
Index: drm/amd/amdgpu/amdgpu_atombios_dp.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_atombios_dp.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -p -u -r1.1 -r1.2
--- drm/amd/amdgpu/amdgpu_atombios_dp.c	27 Aug 2018 14:10:14 -0000	1.1
+++ drm/amd/amdgpu/amdgpu_atombios_dp.c	1 Jan 2019 08:07:47 -0000	1.2
@@ -333,11 +333,11 @@ static void amdgpu_atombios_dp_probe_oui
 		return;
 
 	if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
-		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
+		DRM_DEBUG_KMS("Sink OUI: %02hhx%02hhx%02hhx\n",
 			      buf[0], buf[1], buf[2]);
 
 	if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
-		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
+		DRM_DEBUG_KMS("Branch OUI: %02hhx%02hhx%02hhx\n",
 			      buf[0], buf[1], buf[2]);
 }
 
Index: drm/amd/amdgpu/amdgpu_cz_smc.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_cz_smc.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -p -u -r1.1 -r1.2
--- drm/amd/amdgpu/amdgpu_cz_smc.c	27 Aug 2018 14:10:14 -0000	1.1
+++ drm/amd/amdgpu/amdgpu_cz_smc.c	23 Feb 2019 19:36:15 -0000	1.2
@@ -251,6 +251,7 @@ static int cz_smu_check_finished(struct 
 	case AMDGPU_UCODE_ID_CP_PFP:
 		if (adev->smu.fw_flags & AMDGPU_CPPFP_UCODE_LOADED)
 			return 0;
+		break;
 	case AMDGPU_UCODE_ID_CP_ME:
 		if (adev->smu.fw_flags & AMDGPU_CPME_UCODE_LOADED)
 			return 0;
Index: drm/amd/amdgpu/amdgpu_display.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_display.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -p -u -r1.4 -r1.5
--- drm/amd/amdgpu/amdgpu_display.c	27 Aug 2018 15:22:54 -0000	1.4
+++ drm/amd/amdgpu/amdgpu_display.c	23 Feb 2019 19:56:51 -0000	1.5
@@ -101,7 +101,8 @@ static void amdgpu_flip_work_func(struct
 	 * In practice this won't execute very often unless on very fast
 	 * machines because the time window for this to happen is very small.
 	 */
-	while (amdgpuCrtc->enabled && --repcnt) {
+	if (amdgpuCrtc->enabled) {
+	while (--repcnt) {
 		/* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank
 		 * start in hpos, and to the "fudged earlier" vblank start in
 		 * vpos.
@@ -134,6 +135,7 @@ static void amdgpu_flip_work_func(struct
 				 "hpos %d\n", work->crtc_id, min_udelay,
 				 vblank->framedur_ns / 1000,
 				 vblank->linedur_ns / 1000, stat, vpos, hpos);
+	}
 
 	/* do the flip (mmio) */
 	adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);
Index: drm/amd/amdgpu/amdgpu_gfx_v8_0.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v8_0.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -p -u -r1.1 -r1.2
--- drm/amd/amdgpu/amdgpu_gfx_v8_0.c	27 Aug 2018 14:10:14 -0000	1.1
+++ drm/amd/amdgpu/amdgpu_gfx_v8_0.c	23 Feb 2019 19:37:36 -0000	1.2
@@ -1640,6 +1640,7 @@ static void gfx_v8_0_tiling_mode_table_i
 			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
 			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
 		}
+		break;
 	case CHIP_FIJI:
 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 			switch (reg_offset) {
Index: drm/amd/amdgpu/amdgpu_uvd.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_uvd.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -p -u -r1.3 -r1.4
--- drm/amd/amdgpu/amdgpu_uvd.c	27 Aug 2018 14:04:50 -0000	1.3
+++ drm/amd/amdgpu/amdgpu_uvd.c	1 Jan 2019 08:07:47 -0000	1.4
@@ -159,7 +159,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_dev
 	family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 	version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 	version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
-	DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
+	DRM_INFO("Found UVD firmware Version: %x.%x Family ID: %x\n",
 		version_major, version_minor, family_id);
 
 	adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
Index: drm/amd/amdgpu/amdgpu_vce.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_vce.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -p -u -r1.3 -r1.4
--- drm/amd/amdgpu/amdgpu_vce.c	27 Aug 2018 14:04:50 -0000	1.3
+++ drm/amd/amdgpu/amdgpu_vce.c	1 Jan 2019 08:07:47 -0000	1.4
@@ -144,7 +144,7 @@ int amdgpu_vce_sw_init(struct amdgpu_dev
 	version_major = (ucode_version >> 20) & 0xfff;
 	version_minor = (ucode_version >> 8) & 0xfff;
 	binary_id = ucode_version & 0xff;
-	DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
+	DRM_INFO("Found VCE firmware Version: %x.%x Binary ID: %x\n",
 		version_major, version_minor, binary_id);
 	adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
 				(binary_id << 8));
Index: drm/i915/i915_cmd_parser.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/i915_cmd_parser.c,v
retrieving revision 1.17
retrieving revision 1.18
diff -p -u -r1.17 -r1.18
--- drm/i915/i915_cmd_parser.c	27 Aug 2018 14:50:04 -0000	1.17
+++ drm/i915/i915_cmd_parser.c	9 Sep 2018 03:04:43 -0000	1.18
@@ -555,6 +555,7 @@ static u32 gen7_blt_get_cmd_length_mask(
 	return 0;
 }
 
+__diagused
 static bool validate_cmds_sorted(struct intel_engine_cs *ring,
 				 const struct drm_i915_cmd_table *cmd_tables,
 				 int cmd_table_count)
@@ -611,6 +612,7 @@ static bool check_sorted(int ring_id,
 	return ret;
 }
 
+__diagused
 static bool validate_regs_sorted(struct intel_engine_cs *ring)
 {
 	return check_sorted(ring->id, ring->reg_table, ring->reg_count) &&
Index: drm/i915/i915_dma.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/i915_dma.c,v
retrieving revision 1.25
retrieving revision 1.27
diff -p -u -r1.25 -r1.27
--- drm/i915/i915_dma.c	28 Aug 2018 03:41:38 -0000	1.25
+++ drm/i915/i915_dma.c	21 Sep 2018 11:49:16 -0000	1.27
@@ -693,7 +693,8 @@ static void gen9_sseu_info_init(struct d
 	 * supports EU power gating on devices with more than one EU
 	 * pair per subslice.
 	*/
-	info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1));
+	info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
+			       (info->slice_total > 1));
 	info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
 	info->has_eu_pg = (info->eu_per_subslice > 2);
 }
@@ -704,7 +705,7 @@ static void broadwell_sseu_info_init(str
 	struct intel_device_info *info;
 	const int s_max = 3, ss_max = 3, eu_max = 8;
 	int s, ss;
-	u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
+	u32 fuse2, eu_disable[3], s_enable, ss_disable;
 
 	fuse2 = I915_READ(GEN8_FUSE2);
 	s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
Index: drm/i915/i915_drv.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.c,v
retrieving revision 1.15
retrieving revision 1.16
diff -p -u -r1.15 -r1.16
--- drm/i915/i915_drv.c	27 Aug 2018 15:22:54 -0000	1.15
+++ drm/i915/i915_drv.c	13 Sep 2018 08:25:55 -0000	1.16
@@ -406,6 +406,34 @@ static const struct intel_device_info in
 	IVB_CURSOR_OFFSETS,
 };
 
+static const struct intel_device_info intel_kabylake_info = {
+	.is_kabylake = 1,
+	.gen = 9,
+	.num_pipes = 3,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+	.has_llc = 1,
+	.has_ddi = 1,
+	.has_fpga_dbg = 1,
+	.has_fbc = 1,
+	GEN_DEFAULT_PIPEOFFSETS,
+	IVB_CURSOR_OFFSETS,
+};
+
+static const struct intel_device_info intel_kabylake_gt3_info = {
+	.is_kabylake = 1,
+	.gen = 9,
+	.num_pipes = 3,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+	.has_llc = 1,
+	.has_ddi = 1,
+	.has_fpga_dbg = 1,
+	.has_fbc = 1,
+	GEN_DEFAULT_PIPEOFFSETS,
+	IVB_CURSOR_OFFSETS,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
@@ -446,7 +474,13 @@ static const struct intel_device_info in
 	INTEL_SKL_GT1_IDS(&intel_skylake_info),	\
 	INTEL_SKL_GT2_IDS(&intel_skylake_info),	\
 	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),	\
-	INTEL_BXT_IDS(&intel_broxton_info)
+	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),	\
+	INTEL_BXT_IDS(&intel_broxton_info),	\
+	INTEL_KBL_GT1_IDS(&intel_kabylake_info),	\
+	INTEL_KBL_GT2_IDS(&intel_kabylake_info),	\
+	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),	\
+	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info)
+
 
 static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_PCI_IDS,
@@ -475,7 +509,7 @@ static enum intel_pch intel_virt_detect_
 	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 		ret = PCH_LPT;
 		DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
-	} else if (IS_SKYLAKE(dev)) {
+	} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		ret = PCH_SPT;
 		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 	}
@@ -544,11 +578,17 @@ void intel_detect_pch(struct drm_device 
 			} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_SPT;
 				DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
-				WARN_ON(!IS_SKYLAKE(dev));
+				WARN_ON(!IS_SKYLAKE(dev) &&
+					!IS_KABYLAKE(dev));
 			} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_SPT;
 				DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
-				WARN_ON(!IS_SKYLAKE(dev));
+				WARN_ON(!IS_SKYLAKE(dev) &&
+					!IS_KABYLAKE(dev));
+			} else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
+				dev_priv->pch_type = PCH_KBP;
+				DRM_DEBUG_KMS("Found KabyPoint PCH\n");
+				WARN_ON(!IS_KABYLAKE(dev_priv));
 			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 				    pch->subsystem_vendor == 0x1af4 &&
Index: drm/i915/i915_drv.h
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h,v
retrieving revision 1.27
retrieving revision 1.28
diff -p -u -r1.27 -r1.28
--- drm/i915/i915_drv.h	27 Aug 2018 15:22:54 -0000	1.27
+++ drm/i915/i915_drv.h	13 Sep 2018 08:25:55 -0000	1.28
@@ -800,6 +800,7 @@ struct intel_csr {
 	func(is_valleyview) sep \
 	func(is_haswell) sep \
 	func(is_skylake) sep \
+	func(is_kabylake) sep \
 	func(is_preliminary) sep \
 	func(has_fbc) sep \
 	func(has_pipe_cxsr) sep \
@@ -1027,6 +1028,7 @@ enum intel_pch {
 	PCH_CPT,	/* Cougarpoint PCH */
 	PCH_LPT,	/* Lynxpoint PCH */
 	PCH_SPT,        /* Sunrisepoint PCH */
+	PCH_KBP,	/* Kabypoint PCH */
 	PCH_NOP,
 };
 
@@ -2521,6 +2523,16 @@ struct drm_i915_cmd_table {
 #define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
 #define INTEL_REVID(p)	(__I915__(p)->dev->pdev->revision)
 
+#define REVID_FOREVER	(0xff)
+
+/*
+ * Return true if revision is in range [since,until] inclusive.
+ *
+ * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
+ */
+#define IS_REVID(p, since, until) \
+	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
+
 #define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)
 #define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)
 #define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
@@ -2544,10 +2556,12 @@ struct drm_i915_cmd_table {
 				 INTEL_DEVID(dev) == 0x015a)
 #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
 #define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
-#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
+#define IS_HASWELL(dev)		(INTEL_INFO(dev)->is_haswell)
 #define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
-#define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
-#define IS_BROXTON(dev)	(!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
+#define IS_SKYLAKE(dev)		(INTEL_INFO(dev)->is_skylake)
+#define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
+#define IS_BROXTON(dev)		(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev) && \
+				 IS_GEN9(dev))
 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
 #define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
 				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
@@ -2575,6 +2589,14 @@ struct drm_i915_cmd_table {
 #define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \
 				 INTEL_DEVID(dev) == 0x1915 || \
 				 INTEL_DEVID(dev) == 0x191E)
+#define IS_KBL_ULT(dev)		(INTEL_DEVID(dev) == 0x5906 || \
+				 INTEL_DEVID(dev) == 0x5913 || \
+				 INTEL_DEVID(dev) == 0x5916 || \
+				 INTEL_DEVID(dev) == 0x5921 || \
+				 INTEL_DEVID(dev) == 0x5926)
+#define IS_KBL_ULX(dev)		(INTEL_DEVID(dev) == 0x590E || \
+				 INTEL_DEVID(dev) == 0x5915 || \
+				 INTEL_DEVID(dev) == 0x591E)
 #define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \
 				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
 #define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \
@@ -2589,10 +2611,23 @@ struct drm_i915_cmd_table {
 #define SKL_REVID_E0		(0x4)
 #define SKL_REVID_F0		(0x5)
 
+#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
+
 #define BXT_REVID_A0		(0x0)
+#define BXT_REVID_A1		(0x1)
 #define BXT_REVID_B0		(0x3)
 #define BXT_REVID_C0		(0x9)
 
+#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
+
+#define KBL_REVID_A0		(0x0)
+#define KBL_REVID_B0		(0x1)
+#define KBL_REVID_C0		(0x2)
+#define KBL_REVID_D0		(0x3)
+#define KBL_REVID_E0		(0x4)
+
+#define IS_KBL_REVID(p, since, until) (IS_KABYLAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
@@ -2689,10 +2724,12 @@ struct drm_i915_cmd_table {
 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
 #define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
+#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
 #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
 
 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
+#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
Index: drm/i915/i915_gem_stolen.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem_stolen.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -p -u -r1.10 -r1.11
--- drm/i915/i915_gem_stolen.c	27 Aug 2018 07:20:39 -0000	1.10
+++ drm/i915/i915_gem_stolen.c	13 Sep 2018 08:25:55 -0000	1.11
@@ -465,7 +465,8 @@ int i915_gem_init_stolen(struct drm_devi
 					 &reserved_size);
 		break;
 	default:
-		if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
+		if (IS_BROADWELL(dev_priv) ||
+		    IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev))
 			bdw_get_stolen_reserved(dev_priv, &reserved_base,
 						&reserved_size);
 		else
Index: drm/i915/i915_irq.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c,v
retrieving revision 1.16
retrieving revision 1.17
diff -p -u -r1.16 -r1.17
--- drm/i915/i915_irq.c	27 Aug 2018 14:52:56 -0000	1.16
+++ drm/i915/i915_irq.c	13 Sep 2018 08:25:55 -0000	1.17
@@ -2381,7 +2381,7 @@ static irqreturn_t gen8_irq_handler(DRM_
 			I915_WRITE(SDEIIR, pch_iir);
 			ret = IRQ_HANDLED;
 
-			if (HAS_PCH_SPT(dev_priv))
+			if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
 				spt_irq_handler(dev, pch_iir);
 			else
 				cpt_irq_handler(dev, pch_iir);
@@ -4572,7 +4572,7 @@ void intel_irq_init(struct drm_i915_priv
 		dev->driver->disable_vblank = gen8_disable_vblank;
 		if (IS_BROXTON(dev))
 			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
-		else if (HAS_PCH_SPT(dev))
+		else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
 			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
 		else
 			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
Index: drm/i915/i915_reg.h
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -p -u -r1.4 -r1.5
--- drm/i915/i915_reg.h	27 Aug 2018 07:06:25 -0000	1.4
+++ drm/i915/i915_reg.h	13 Sep 2018 08:25:55 -0000	1.5
@@ -1590,6 +1590,12 @@ enum skl_disp_power_wells {
 
 #define GEN7_TLB_RD_ADDR	0x4700
 
+#define GAMT_CHKN_BIT_REG	0x4ab8
+#define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING     (1<<28)
+
+#define GEN9_GAMT_ECO_REG_RW_IA	0x4ab0
+#define   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS	(1<<18)
+
 #if 0
 #define PRB0_TAIL	0x02030
 #define PRB0_HEAD	0x02034
@@ -5921,6 +5927,9 @@ enum skl_disp_power_wells {
 #define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
+#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
+#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
+#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
 
 #define FF_SLICE_CS_CHICKEN2			0x20e4
 #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
@@ -5930,6 +5939,7 @@ enum skl_disp_power_wells {
 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
 # define GEN9_RHWO_OPTIMIZATION_DISABLE		(1<<14)
 #define COMMON_SLICE_CHICKEN2			0x7014
+# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
 
 #define HIZ_CHICKEN					0x7018
@@ -6766,6 +6776,7 @@ enum skl_disp_power_wells {
 
 #define GEN7_UCGCTL4				0x940c
 #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1<<25)
+#define  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE	(1<<14)
 
 #define GEN6_RCGCTL1				0x9410
 #define GEN6_RCGCTL2				0x9414
Index: drm/i915/intel_csr.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/intel_csr.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -p -u -r1.4 -r1.5
--- drm/i915/intel_csr.c	27 Aug 2018 15:09:35 -0000	1.4
+++ drm/i915/intel_csr.c	13 Sep 2018 08:25:55 -0000	1.5
@@ -48,9 +48,11 @@ __KERNEL_RCSID(0, "$NetBSD$");
  * be moved to FW_FAILED.
  */
 
+#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
 #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
 
+MODULE_FIRMWARE(I915_CSR_KBL);
 MODULE_FIRMWARE(I915_CSR_SKL);
 MODULE_FIRMWARE(I915_CSR_BXT);
 
@@ -184,6 +186,14 @@ struct stepping_info {
 	char substepping;
 };
 
+/*
+ * Kabylake derivated from Skylake H0, so SKL H0
+ * is the right firmware for KBL A0 (revid 0).
+ */
+static const struct stepping_info kbl_stepping_info[] = {
+	{'H', '0'}, {'I', '0'}
+};
+
 static const struct stepping_info skl_stepping_info[] = {
 		{'A', '0'}, {'B', '0'}, {'C', '0'},
 		{'D', '0'}, {'E', '0'}, {'F', '0'},
@@ -198,7 +208,10 @@ static struct stepping_info bxt_stepping
 
 static char intel_get_stepping(struct drm_device *dev)
 {
-	if (IS_SKYLAKE(dev) && (dev->pdev->revision <
+	if (IS_KABYLAKE(dev) && (dev->pdev->revision <
+			ARRAY_SIZE(kbl_stepping_info)))
+		return kbl_stepping_info[dev->pdev->revision].stepping;
+	else if (IS_SKYLAKE(dev) && (dev->pdev->revision <
 			ARRAY_SIZE(skl_stepping_info)))
 		return skl_stepping_info[dev->pdev->revision].stepping;
 	else if (IS_BROXTON(dev) && (dev->pdev->revision <
@@ -210,7 +223,10 @@ static char intel_get_stepping(struct dr
 
 static char intel_get_substepping(struct drm_device *dev)
 {
-	if (IS_SKYLAKE(dev) && (dev->pdev->revision <
+	if (IS_KABYLAKE(dev) && (dev->pdev->revision <
+			ARRAY_SIZE(kbl_stepping_info)))
+		return kbl_stepping_info[dev->pdev->revision].substepping;
+	else if (IS_SKYLAKE(dev) && (dev->pdev->revision <
 			ARRAY_SIZE(skl_stepping_info)))
 		return skl_stepping_info[dev->pdev->revision].substepping;
 	else if (IS_BROXTON(dev) && (dev->pdev->revision <
@@ -436,7 +452,9 @@ void intel_csr_ucode_init(struct drm_dev
 	if (!HAS_CSR(dev))
 		return;
 
-	if (IS_SKYLAKE(dev))
+	if (IS_KABYLAKE(dev))
+		csr->fw_path = I915_CSR_KBL;
+	else if (IS_SKYLAKE(dev))
 		csr->fw_path = I915_CSR_SKL;
 	else if (IS_BROXTON(dev_priv))
 		csr->fw_path = I915_CSR_BXT;
Index: drm/i915/intel_ddi.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/intel_ddi.c,v
retrieving revision 1.7
retrieving revision 1.10
diff -p -u -r1.7 -r1.10
--- drm/i915/intel_ddi.c	27 Aug 2018 07:26:08 -0000	1.7
+++ drm/i915/intel_ddi.c	19 Feb 2019 00:30:16 -0000	1.10
@@ -360,10 +360,10 @@ static const struct ddi_buf_trans *skl_g
 {
 	const struct ddi_buf_trans *ddi_translations;
 
-	if (IS_SKL_ULX(dev)) {
+	if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
 		ddi_translations = skl_y_ddi_translations_dp;
 		*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
-	} else if (IS_SKL_ULT(dev)) {
+	} else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) {
 		ddi_translations = skl_u_ddi_translations_dp;
 		*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 	} else {
@@ -380,7 +380,7 @@ static const struct ddi_buf_trans *skl_g
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	const struct ddi_buf_trans *ddi_translations;
 
-	if (IS_SKL_ULX(dev)) {
+	if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
 		if (dev_priv->edp_low_vswing) {
 			ddi_translations = skl_y_ddi_translations_edp;
 			*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
@@ -388,7 +388,7 @@ static const struct ddi_buf_trans *skl_g
 			ddi_translations = skl_y_ddi_translations_dp;
 			*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 		}
-	} else if (IS_SKL_ULT(dev)) {
+	} else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) {
 		if (dev_priv->edp_low_vswing) {
 			ddi_translations = skl_u_ddi_translations_edp;
 			*n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
@@ -415,7 +415,7 @@ skl_get_buf_trans_hdmi(struct drm_device
 {
 	const struct ddi_buf_trans *ddi_translations;
 
-	if (IS_SKL_ULX(dev)) {
+	if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
 		ddi_translations = skl_y_ddi_translations_hdmi;
 		*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 	} else {
@@ -455,7 +455,7 @@ static void intel_prepare_ddi_buffers(st
 		bxt_ddi_vswing_sequence(dev, hdmi_level, port,
 					INTEL_OUTPUT_HDMI);
 		return;
-	} else if (IS_SKYLAKE(dev)) {
+	} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		ddi_translations_fdi = NULL;
 		ddi_translations_dp =
 				skl_get_buf_trans_dp(dev, &n_dp_entries);
@@ -1199,7 +1199,7 @@ void intel_ddi_clock_get(struct intel_en
 
 	if (INTEL_INFO(dev)->gen <= 8)
 		hsw_ddi_clock_get(encoder, pipe_config);
-	else if (IS_SKYLAKE(dev))
+	else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 		skl_ddi_clock_get(encoder, pipe_config);
 	else if (IS_BROXTON(dev))
 		bxt_ddi_clock_get(encoder, pipe_config);
@@ -1796,7 +1796,7 @@ bool intel_ddi_pll_select(struct intel_c
 	struct intel_encoder *intel_encoder =
 		intel_ddi_get_crtc_new_encoder(crtc_state);
 
-	if (IS_SKYLAKE(dev))
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 		return skl_ddi_pll_select(intel_crtc, crtc_state,
 					  intel_encoder);
 	else if (IS_BROXTON(dev))
@@ -2279,7 +2279,7 @@ uint32_t ddi_signal_levels(struct intel_
 
 	level = translate_signal_level(signal_levels);
 
-	if (IS_SKYLAKE(dev))
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 		skl_ddi_set_iboost(dev, level, port, encoder->type);
 	else if (IS_BROXTON(dev))
 		bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
@@ -2302,7 +2302,7 @@ static void intel_ddi_pre_enable(struct 
 		intel_edp_panel_on(intel_dp);
 	}
 
-	if (IS_SKYLAKE(dev)) {
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		uint32_t dpll = crtc->config->ddi_pll_sel;
 		uint32_t val;
 
@@ -2397,7 +2397,7 @@ static void intel_ddi_post_disable(struc
 		intel_edp_panel_off(intel_dp);
 	}
 
-	if (IS_SKYLAKE(dev))
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
 					DPLL_CTRL2_DDI_CLK_OFF(port)));
 	else if (INTEL_INFO(dev)->gen < 9)
@@ -3008,14 +3008,14 @@ void intel_ddi_pll_init(struct drm_devic
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t val = I915_READ(LCPLL_CTL);
 
-	if (IS_SKYLAKE(dev))
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 		skl_shared_dplls_init(dev_priv);
 	else if (IS_BROXTON(dev))
 		bxt_shared_dplls_init(dev_priv);
 	else
 		hsw_shared_dplls_init(dev_priv);
 
-	if (IS_SKYLAKE(dev)) {
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		int cdclk_freq;
 
 		cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
Index: drm/i915/intel_display.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c,v
retrieving revision 1.22
retrieving revision 1.26
diff -p -u -r1.22 -r1.26
--- drm/i915/intel_display.c	2 Sep 2018 17:36:57 -0000	1.22
+++ drm/i915/intel_display.c	19 Feb 2019 00:30:16 -0000	1.26
@@ -2039,7 +2039,7 @@ static void lpt_enable_pch_transcoder(st
 
 	/* FDI must be feeding us bits for PCH ports */
 	assert_fdi_tx_enabled(dev_priv, (enum i915_pipe) cpu_transcoder);
-	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
+	assert_fdi_rx_enabled(dev_priv, (enum i915_pipe) TRANSCODER_A);
 
 	/* Workaround: set timing override bit. */
 	val = I915_READ(TRANS_CHICKEN2(PIPE_A));
@@ -2132,7 +2132,7 @@ static void intel_enable_pipe(struct int
 	assert_sprites_disabled(dev_priv, pipe);
 
 	if (HAS_PCH_LPT(dev_priv->dev))
-		pch_transcoder = TRANSCODER_A;
+		pch_transcoder = (enum i915_pipe)TRANSCODER_A;
 	else
 		pch_transcoder = pipe;
 
@@ -4307,7 +4307,7 @@ static void lpt_pch_enable(struct drm_cr
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
 
-	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
+	assert_pch_transcoder_disabled(dev_priv, (enum i915_pipe) TRANSCODER_A);
 
 	lpt_program_iclkip(crtc);
 
@@ -5465,7 +5465,7 @@ static void intel_update_max_cdclk(struc
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (IS_SKYLAKE(dev)) {
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
 
 		if (limit == SKL_DFSM_CDCLK_LIMIT_675)
@@ -9905,7 +9905,7 @@ static void haswell_get_ddi_port_state(s
 
 	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
 
-	if (IS_SKYLAKE(dev))
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 		skylake_get_ddi_pll(dev_priv, port, pipe_config);
 	else if (IS_BROXTON(dev))
 		bxt_get_ddi_pll(dev_priv, port, pipe_config);
@@ -12161,7 +12161,7 @@ static void intel_dump_pipe_config(struc
 			      pipe_config->dpll_hw_state.pll9,
 			      pipe_config->dpll_hw_state.pll10,
 			      pipe_config->dpll_hw_state.pcsdw12);
-	} else if (IS_SKYLAKE(dev)) {
+	} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
 			      "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
 			      pipe_config->ddi_pll_sel,
@@ -14185,7 +14185,7 @@ static void intel_setup_outputs(struct d
 		 */
 		found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
 		/* WaIgnoreDDIAStrap: skl */
-		if (found || IS_SKYLAKE(dev))
+		if (found || (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)))
 			intel_ddi_init(dev, PORT_A);
 
 		/* DDI B, C and D detection is indicated by the SFUSE_STRAP
@@ -14201,7 +14201,7 @@ static void intel_setup_outputs(struct d
 		/*
 		 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
 		 */
-		if (IS_SKYLAKE(dev) &&
+		if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
 		    (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
 		     dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
 		     dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
@@ -14660,7 +14660,7 @@ static void intel_init_display(struct dr
 	}
 
 	/* Returns the core display clock speed */
-	if (IS_SKYLAKE(dev))
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 		dev_priv->display.get_display_clock_speed =
 			skylake_get_display_clock_speed;
 	else if (IS_BROXTON(dev))
Index: drm/i915/intel_dp.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/intel_dp.c,v
retrieving revision 1.18
retrieving revision 1.19
diff -p -u -r1.18 -r1.19
--- drm/i915/intel_dp.c	2 Sep 2018 17:36:57 -0000	1.18
+++ drm/i915/intel_dp.c	13 Sep 2018 08:25:55 -0000	1.19
@@ -1050,7 +1050,7 @@ intel_dp_aux_init(struct intel_dp *intel
 	/* On SKL we don't have Aux for port E so we rely on VBT to set
 	 * a proper alternate aux channel.
 	 */
-	if (IS_SKYLAKE(dev) && port == PORT_E) {
+	if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && port == PORT_E) {
 		switch (info->alternate_aux_channel) {
 		case DP_AUX_B:
 			porte_aux_ctl_reg = DPB_AUX_CH_CTL;
@@ -1248,7 +1248,7 @@ intel_dp_source_rates(struct drm_device 
 	if (IS_BROXTON(dev)) {
 		*source_rates = bxt_rates;
 		size = ARRAY_SIZE(bxt_rates);
-	} else if (IS_SKYLAKE(dev)) {
+	} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		*source_rates = skl_rates;
 		size = ARRAY_SIZE(skl_rates);
 	} else {
@@ -1568,7 +1568,7 @@ found:
 				&pipe_config->dp_m2_n2);
 	}
 
-	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
+	if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
 		skl_edp_set_pll_config(pipe_config);
 	else if (IS_BROXTON(dev))
 		/* handled in ddi */;
Index: drm/i915/intel_fbc.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/intel_fbc.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -p -u -r1.3 -r1.4
--- drm/i915/intel_fbc.c	27 Aug 2018 07:21:33 -0000	1.3
+++ drm/i915/intel_fbc.c	13 Sep 2018 08:25:55 -0000	1.4
@@ -586,7 +586,8 @@ static int find_compression_threshold(st
 	 * reserved range size, so it always assumes the maximum (8mb) is used.
 	 * If we enable FBC using a CFB on that memory range we'll get FIFO
 	 * underruns, even if that range is not reserved by the BIOS. */
-	if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
+	if (IS_BROADWELL(dev_priv) ||
+	    IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 		end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024;
 	else
 		end = dev_priv->gtt.stolen_usable_size;
Index: drm/i915/intel_guc_loader.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/intel_guc_loader.c,v
retrieving revision 1.12
retrieving revision 1.13
diff -p -u -r1.12 -r1.13
--- drm/i915/intel_guc_loader.c	27 Aug 2018 15:09:35 -0000	1.12
+++ drm/i915/intel_guc_loader.c	13 Sep 2018 08:25:55 -0000	1.13
@@ -69,6 +69,9 @@ __KERNEL_RCSID(0, "$NetBSD$");
 #define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin"
 MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
 
+#define I915_KBL_GUC_UCODE "i915/kbl_guc_ver9_14.bin"
+MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+
 /* User-friendly representation of an enum */
 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
 {
@@ -589,6 +592,10 @@ void intel_guc_ucode_init(struct drm_dev
 		fw_path = I915_SKL_GUC_UCODE;
 		guc_fw->guc_fw_major_wanted = 4;
 		guc_fw->guc_fw_minor_wanted = 3;
+	} else if (IS_KABYLAKE(dev)) {
+		fw_path = I915_KBL_GUC_UCODE;
+		guc_fw->guc_fw_major_wanted = 9;
+		guc_fw->guc_fw_minor_wanted = 14;
 	} else {
 		i915.enable_guc_submission = false;
 		fw_path = "";	/* unknown device */
Index: drm/i915/intel_i2c.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/intel_i2c.c,v
retrieving revision 1.16
retrieving revision 1.17
diff -p -u -r1.16 -r1.17
--- drm/i915/intel_i2c.c	27 Aug 2018 06:16:37 -0000	1.16
+++ drm/i915/intel_i2c.c	13 Sep 2018 08:25:55 -0000	1.17
@@ -80,7 +80,7 @@ static const struct gmbus_pin *get_gmbus
 {
 	if (IS_BROXTON(dev_priv))
 		return &gmbus_pins_bxt[pin];
-	else if (IS_SKYLAKE(dev_priv))
+	else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 		return &gmbus_pins_skl[pin];
 	else if (IS_BROADWELL(dev_priv))
 		return &gmbus_pins_bdw[pin];
@@ -95,7 +95,7 @@ bool intel_gmbus_is_valid_pin(struct drm
 
 	if (IS_BROXTON(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_bxt);
-	else if (IS_SKYLAKE(dev_priv))
+	else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_skl);
 	else if (IS_BROADWELL(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_bdw);
Index: drm/i915/intel_mocs.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/intel_mocs.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -p -u -r1.2 -r1.3
--- drm/i915/intel_mocs.c	27 Aug 2018 04:58:24 -0000	1.2
+++ drm/i915/intel_mocs.c	13 Sep 2018 08:25:55 -0000	1.3
@@ -148,7 +148,7 @@ static bool get_mocs_settings(struct drm
 {
 	bool result = false;
 
-	if (IS_SKYLAKE(dev)) {
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		table->size  = ARRAY_SIZE(skylake_mocs_table);
 		table->table = skylake_mocs_table;
 		result = true;
Index: drm/i915/intel_panel.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/intel_panel.c,v
retrieving revision 1.10
retrieving revision 1.12
diff -p -u -r1.10 -r1.12
--- drm/i915/intel_panel.c	27 Aug 2018 07:27:16 -0000	1.10
+++ drm/i915/intel_panel.c	6 Oct 2018 15:33:35 -0000	1.12
@@ -432,6 +432,7 @@ static uint32_t scale(uint32_t source_va
 	return target_val;
 }
 
+#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
 /* Scale user_level in range [0..user_max] to [hw_min..hw_max]. */
 static inline u32 scale_user_to_hw(struct intel_connector *connector,
 				   u32 user_level, u32 user_max)
@@ -441,6 +442,7 @@ static inline u32 scale_user_to_hw(struc
 	return scale(user_level, 0, user_max,
 		     panel->backlight.min, panel->backlight.max);
 }
+#endif
 
 /* Scale user_level in range [0..user_max] to [0..hw_max], clamping the result
  * to [hw_min..hw_max]. */
@@ -456,6 +458,7 @@ static inline u32 clamp_user_to_hw(struc
 	return hw_level;
 }
 
+#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
 /* Scale hw_level in range [hw_min..hw_max] to [0..user_max]. */
 static inline u32 scale_hw_to_user(struct intel_connector *connector,
 				   u32 hw_level, u32 user_max)
@@ -465,6 +468,7 @@ static inline u32 scale_hw_to_user(struc
 	return scale(hw_level, panel->backlight.min, panel->backlight.max,
 		     0, user_max);
 }
+#endif
 
 static u32 intel_panel_compute_brightness(struct intel_connector *connector,
 					  u32 val)
@@ -1782,7 +1786,8 @@ intel_panel_init_backlight_funcs(struct 
 		panel->backlight.disable = bxt_disable_backlight;
 		panel->backlight.set = bxt_set_backlight;
 		panel->backlight.get = bxt_get_backlight;
-	} else if (HAS_PCH_LPT(dev) || HAS_PCH_SPT(dev)) {
+	} else if (HAS_PCH_LPT(dev) || HAS_PCH_SPT(dev) ||
+		   HAS_PCH_KBP(dev)) {
 		panel->backlight.setup = lpt_setup_backlight;
 		panel->backlight.enable = lpt_enable_backlight;
 		panel->backlight.disable = lpt_disable_backlight;
Index: drm/i915/intel_pm.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c,v
retrieving revision 1.15
retrieving revision 1.16
diff -p -u -r1.15 -r1.16
--- drm/i915/intel_pm.c	27 Aug 2018 15:09:35 -0000	1.15
+++ drm/i915/intel_pm.c	13 Sep 2018 08:25:55 -0000	1.16
@@ -4727,7 +4727,8 @@ static void gen6_init_rps_frequencies(st
 	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;
 
 	dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
-	if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
+	if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
+	    IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		ret = sandybridge_pcode_read(dev_priv,
 					HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
 					&ddcc_status);
@@ -4739,7 +4740,7 @@ static void gen6_init_rps_frequencies(st
 					dev_priv->rps.max_freq);
 	}
 
-	if (IS_SKYLAKE(dev)) {
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		/* Store the frequency values in 16.66 MHZ units, which is
 		   the natural hardware unit for SKL */
 		dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
@@ -5102,7 +5103,7 @@ static void __gen6_update_ring_freq(stru
 	/* convert DDR frequency from units of 266.6MHz to bandwidth */
 	min_ring_freq = mult_frac(min_ring_freq, 8, 3);
 
-	if (IS_SKYLAKE(dev)) {
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		/* Convert GT frequency to 50 HZ units */
 		min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
 		max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
@@ -5120,7 +5121,7 @@ static void __gen6_update_ring_freq(stru
 		int diff = max_gpu_freq - gpu_freq;
 		unsigned int ia_freq = 0, ring_freq = 0;
 
-		if (IS_SKYLAKE(dev)) {
+		if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 			/*
 			 * ring_freq = 2 * GT. ring_freq is in 100MHz units
 			 * No floor required for ring frequency on SKL.
@@ -6250,7 +6251,7 @@ static void intel_gen6_powersave_work(st
 	} else if (INTEL_INFO(dev)->gen >= 9) {
 		gen9_enable_rc6(dev);
 		gen9_enable_rps(dev);
-		if (IS_SKYLAKE(dev))
+		if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 			__gen6_update_ring_freq(dev);
 	} else if (IS_BROADWELL(dev)) {
 		gen8_enable_rps(dev);
Index: drm/i915/intel_ringbuffer.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/intel_ringbuffer.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -p -u -r1.8 -r1.9
--- drm/i915/intel_ringbuffer.c	27 Aug 2018 07:29:50 -0000	1.8
+++ drm/i915/intel_ringbuffer.c	13 Sep 2018 08:25:55 -0000	1.9
@@ -993,7 +993,7 @@ static int gen9_init_workarounds(struct 
 	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 
 	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
-	if (IS_SKYLAKE(dev) ||
+	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ||
 	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
 		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 				  GEN8_SAMPLER_POWER_BYPASS_DIS);
@@ -1149,6 +1149,65 @@ static int bxt_init_workarounds(struct i
 	return 0;
 }
 
+static int kbl_init_workarounds(struct intel_engine_cs *ring)
+{
+	struct drm_device *dev = ring->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int ret;
+
+	ret = gen9_init_workarounds(ring);
+	if (ret)
+		return ret;
+
+	/* WaEnableGapsTsvCreditFix:kbl */
+	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+				   GEN9_GAPS_TSV_CREDIT_DISABLE));
+
+	/* WaDisableDynamicCreditSharing:kbl */
+	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+		WA_SET_BIT(GAMT_CHKN_BIT_REG,
+			   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
+
+	/* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
+	if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
+		WA_SET_BIT_MASKED(HDC_CHICKEN0,
+				  HDC_FENCE_DEST_SLM_DISABLE);
+
+	/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
+	 * involving this register should also be added to WA batch as required.
+	 */
+	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
+		/* WaDisableLSQCROPERFforOCL:kbl */
+		I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+			   GEN8_LQSC_RO_PERF_DIS);
+
+	/* WaToEnableHwFixForPushConstHWBug:kbl */
+	if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER))
+		WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+				  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+
+	/* WaDisableGafsUnitClkGating:kbl */
+	WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaDisableSbeCacheDispatchPortSharing:kbl */
+	WA_SET_BIT_MASKED(
+		GEN7_HALF_SLICE_CHICKEN1,
+		GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+
+	/* WaInPlaceDecompressionHang:kbl */
+	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
+		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
+#ifdef notyet
+	/* WaDisableLSQCROPERFforOCL:kbl */
+	ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
 int init_workarounds_ring(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
@@ -1170,6 +1229,9 @@ int init_workarounds_ring(struct intel_e
 	if (IS_BROXTON(dev))
 		return bxt_init_workarounds(ring);
 
+	if (IS_KABYLAKE(dev))
+		return kbl_init_workarounds(ring);
+
 	return 0;
 }
 
Index: drm/i915/intel_runtime_pm.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/intel_runtime_pm.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -p -u -r1.5 -r1.6
--- drm/i915/intel_runtime_pm.c	27 Aug 2018 07:30:37 -0000	1.5
+++ drm/i915/intel_runtime_pm.c	13 Sep 2018 08:25:55 -0000	1.6
@@ -55,7 +55,7 @@ __KERNEL_RCSID(0, "$NetBSD$");
  */
 
 #define GEN9_ENABLE_DC5(dev) 0
-#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
+#define SKL_ENABLE_DC6(dev) (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 
 #define for_each_power_well(i, power_well, domain_mask, power_domains)	\
 	for (i = 0;							\
@@ -493,7 +493,8 @@ static void assert_can_enable_dc5(struct
 	bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 					SKL_DISP_PW_2);
 
-	WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
+	WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
+		  "Platform doesn't support DC5.\n");
 	WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 	WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 
@@ -556,7 +557,8 @@ static void assert_can_enable_dc6(struct
 {
 	struct drm_device *dev = dev_priv->dev;
 
-	WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");
+	WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
+		  "Platform doesn't support DC6.\n");
 	WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 	WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 		  "Backlight is not disabled.\n");
@@ -686,7 +688,7 @@ static void skl_set_power_well(struct dr
 		}
 	} else {
 		if (enable_requested) {
-			if (IS_SKYLAKE(dev) &&
+			if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
 				(power_well->data == SKL_DISP_PW_1) &&
 				(intel_csr_load_status_get(dev_priv) == FW_LOADED))
 				DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n");
@@ -1848,7 +1850,7 @@ sanitize_disable_power_well_option(const
 	if (disable_power_well >= 0)
 		return !!disable_power_well;
 
-	if (IS_SKYLAKE(dev_priv)) {
+	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 		DRM_DEBUG_KMS("Disabling display power well support\n");
 		return 0;
 	}
@@ -1891,7 +1893,7 @@ int intel_power_domains_init(struct drm_
 		set_power_wells(power_domains, hsw_power_wells);
 	} else if (IS_BROADWELL(dev_priv->dev)) {
 		set_power_wells(power_domains, bdw_power_wells);
-	} else if (IS_SKYLAKE(dev_priv->dev)) {
+	} else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) {
 		set_power_wells(power_domains, skl_power_wells);
 	} else if (IS_BROXTON(dev_priv->dev)) {
 		set_power_wells(power_domains, bxt_power_wells);
Index: drm/nouveau/nouveau_bo.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/nouveau/nouveau_bo.c,v
retrieving revision 1.12
retrieving revision 1.15
diff -p -u -r1.12 -r1.15
--- drm/nouveau/nouveau_bo.c	27 Aug 2018 15:22:54 -0000	1.12
+++ drm/nouveau/nouveau_bo.c	19 Feb 2019 00:30:16 -0000	1.15
@@ -543,6 +543,7 @@ nouveau_bo_validate(struct nouveau_bo *n
 #  define	iowrite16_native	fake_iowrite16_native
 #  define	iowrite32_native	fake_iowrite32_native
 
+#ifdef notdef
 static inline uint16_t
 ioread16_native(const void __iomem *ptr)
 {
@@ -553,6 +554,7 @@ ioread16_native(const void __iomem *ptr)
 
 	return v;
 }
+#endif
 
 static inline uint32_t
 ioread32_native(const void __iomem *ptr)
Index: drm/nouveau/nouveau_drm.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/nouveau/nouveau_drm.c,v
retrieving revision 1.15
retrieving revision 1.17
diff -p -u -r1.15 -r1.17
--- drm/nouveau/nouveau_drm.c	27 Aug 2018 15:22:54 -0000	1.15
+++ drm/nouveau/nouveau_drm.c	16 Apr 2019 10:00:04 -0000	1.17
@@ -954,7 +954,36 @@ nouveau_ioctls[] = {
 	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH|DRM_RENDER_ALLOW),
 };
 
-#ifndef __NetBSD__		/* XXX nouveau pm */
+#ifdef __NetBSD__
+#include <sys/file.h>
+#include <sys/ioccom.h>
+static int			/* XXX expose to ioc32 */
+nouveau_ioctl_override(struct file *fp, unsigned long cmd, void *data)
+{
+	struct drm_file *file = fp->f_data;
+	struct drm_device *dev = file->minor->dev;
+	int ret;
+
+	ret = pm_runtime_get_sync(dev->dev);
+	if (ret < 0 && ret != -EACCES)
+		/* XXX errno Linux->NetBSD */
+		return -ret;
+
+	switch (DRM_IOCTL_NR(cmd) - DRM_COMMAND_BASE) {
+	case DRM_NOUVEAU_NVIF:
+		/* XXX errno Linux->NetBSD */
+		ret = -usif_ioctl(file, data, IOCPARM_LEN(cmd));
+		break;
+	default:
+		ret = drm_ioctl(fp, cmd, data);
+		break;
+	}
+
+	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_put_autosuspend(dev->dev);
+	return ret;
+}
+#else
 long
 nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 {
@@ -979,7 +1008,9 @@ nouveau_drm_ioctl(struct file *file, uns
 	pm_runtime_put_autosuspend(dev->dev);
 	return ret;
 }
+#endif
 
+#ifndef __NetBSD__
 static const struct file_operations
 nouveau_driver_fops = {
 	.owner = THIS_MODULE,
@@ -1026,6 +1057,7 @@ driver_stub = {
 	.fops = NULL,
 	.mmap_object = &nouveau_ttm_mmap_object,
 	.gem_uvm_ops = &nouveau_gem_uvm_ops,
+	.ioctl_override = nouveau_ioctl_override,
 #else
 	.fops = &nouveau_driver_fops,
 #endif
Index: drm/nouveau/nouveau_fence.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/nouveau/nouveau_fence.c,v
retrieving revision 1.13
retrieving revision 1.14
diff -p -u -r1.13 -r1.14
--- drm/nouveau/nouveau_fence.c	28 Aug 2018 20:59:21 -0000	1.13
+++ drm/nouveau/nouveau_fence.c	16 Apr 2019 10:00:04 -0000	1.14
@@ -334,8 +334,11 @@ nouveau_fence_wait_legacy(struct fence *
 		/* XXX what lock? */
 		/* XXX errno NetBSD->Linux */
 		ret = -kpause("nvfencel", intr, 1, NULL);
-		if (ret)
+		if (ret) {
+			if (ret == -ERESTART)
+				ret = -ERESTARTSYS;
 			return ret;
+		}
 		t = jiffies;
 		if (t >= timeout)
 			return 0;
Index: drm/nouveau/nouveau_nvif.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/nouveau/nouveau_nvif.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -p -u -r1.4 -r1.5
--- drm/nouveau/nouveau_nvif.c	27 Aug 2018 14:47:53 -0000	1.4
+++ drm/nouveau/nouveau_nvif.c	9 Sep 2018 03:10:03 -0000	1.5
@@ -90,7 +90,7 @@ nvkm_client_unmap(void *priv, bus_space_
 	if (tag == client->mmiot &&
 	    client->mmioaddr <= busaddr &&
 	    busaddr - client->mmioaddr <= client->mmiosz) {
-		const bus_size_t offset = busaddr - client->mmioaddr;
+		__diagused const bus_size_t offset = busaddr - client->mmioaddr;
 		KASSERT(size <= client->mmiosz - offset);
 		/* Nothing to do to release a subregion.  */
 		return;
Index: drm/nouveau/nouveau_usif.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/nouveau/nouveau_usif.c,v
retrieving revision 1.5
retrieving revision 1.7
diff -p -u -r1.5 -r1.7
--- drm/nouveau/nouveau_usif.c	27 Aug 2018 07:43:16 -0000	1.5
+++ drm/nouveau/nouveau_usif.c	18 Feb 2019 23:23:41 -0000	1.7
@@ -305,11 +305,17 @@ usif_object_new(struct drm_file *f, void
 }
 
 int
+#ifdef __NetBSD__
+usif_ioctl(struct drm_file *filp, void *data, u32 argc)
+#else
 usif_ioctl(struct drm_file *filp, void __user *user, u32 argc)
+#endif
 {
 	struct nouveau_cli *cli = nouveau_cli(filp);
 	struct nvif_client *client = &cli->base;
+#ifndef __NetBSD__
 	void *data = kmalloc(argc, GFP_KERNEL);
+#endif
 	u32   size = argc;
 	union {
 		struct nvif_ioctl_v0 v0;
@@ -318,10 +324,12 @@ usif_ioctl(struct drm_file *filp, void _
 	u8 owner;
 	int ret;
 
+#ifndef __NetBSD__
 	if (ret = -ENOMEM, !argv)
 		goto done;
 	if (ret = -EFAULT, copy_from_user(argv, user, size))
 		goto done;
+#endif
 
 	if (nvif_unpack(argv->v0, 0, 0, true)) {
 		/* block access to objects not created via this interface */
@@ -366,6 +374,7 @@ usif_ioctl(struct drm_file *filp, void _
 	case NVIF_IOCTL_V0_MAP_NETBSD:
 		/* Kernel-only kludge.  */
 		ret = -EINVAL;
+		break;
 	default:
 		ret = nvif_client_ioctl(client, argv, argc);
 		break;
@@ -385,10 +394,14 @@ usif_ioctl(struct drm_file *filp, void _
 	argv->v0.owner = owner;
 	mutex_unlock(&cli->mutex);
 
+#ifndef __NetBSD__
 	if (copy_to_user(user, argv, argc))
 		ret = -EFAULT;
+#endif
 done:
+#ifndef __NetBSD__
 	kfree(argv);
+#endif
 	return ret;
 }
 
Index: drm/nouveau/nouveau_usif.h
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/nouveau/nouveau_usif.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -p -u -r1.2 -r1.3
--- drm/nouveau/nouveau_usif.h	27 Aug 2018 04:58:24 -0000	1.2
+++ drm/nouveau/nouveau_usif.h	21 Dec 2018 07:51:17 -0000	1.3
@@ -5,7 +5,11 @@
 
 void usif_client_init(struct nouveau_cli *);
 void usif_client_fini(struct nouveau_cli *);
+#ifdef __NetBSD__
+int  usif_ioctl(struct drm_file *, void *, u32);
+#else
 int  usif_ioctl(struct drm_file *, void __user *, u32);
+#endif
 int  usif_notify(const void *, u32, const void *, u32);
 
 #endif
Index: drm/nouveau/nvkm/core/nouveau_nvkm_core_option.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/core/nouveau_nvkm_core_option.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -p -u -r1.3 -r1.4
--- drm/nouveau/nvkm/core/nouveau_nvkm_core_option.c	27 Aug 2018 14:19:47 -0000	1.3
+++ drm/nouveau/nvkm/core/nouveau_nvkm_core_option.c	8 Jan 2019 05:57:34 -0000	1.4
@@ -101,8 +101,6 @@ nvkm_dbgopt(const char *optstr, const ch
 {
 	int mode = 1, level = CONFIG_NOUVEAU_DEBUG_DEFAULT;
 
-	return NV_DBG_DEBUG;
-
 	while (optstr) {
 		int len = strcspn(optstr, ",=");
 		switch (optstr[len]) {
Index: drm/nouveau/nvkm/engine/fifo/nouveau_nvkm_engine_fifo_chan.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/fifo/nouveau_nvkm_engine_fifo_chan.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -p -u -r1.8 -r1.9
--- drm/nouveau/nvkm/engine/fifo/nouveau_nvkm_engine_fifo_chan.c	27 Aug 2018 14:54:33 -0000	1.8
+++ drm/nouveau/nvkm/engine/fifo/nouveau_nvkm_engine_fifo_chan.c	9 Sep 2018 03:12:51 -0000	1.9
@@ -480,7 +480,8 @@ nvkm_fifo_chan_ctor(const struct nvkm_fi
 		bus_space_tag_t mmiot = device->mmiot;
 		bus_space_handle_t mmioh = device->mmioh;
 		bus_size_t mmiosz = device->mmiosz;
-		bus_addr_t mmioaddr = device->func->resource_addr(device, bar);
+		__diagused bus_addr_t mmioaddr =
+		    device->func->resource_addr(device, bar);
 
 		/* Check whether it lies inside the region.  */
 		if (mmiosz < base ||
Index: drm/nouveau/nvkm/subdev/clk/nouveau_nvkm_subdev_clk_gt215.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/nouveau_nvkm_subdev_clk_gt215.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -p -u -r1.3 -r1.4
--- drm/nouveau/nvkm/subdev/clk/nouveau_nvkm_subdev_clk_gt215.c	27 Aug 2018 07:38:56 -0000	1.3
+++ drm/nouveau/nvkm/subdev/clk/nouveau_nvkm_subdev_clk_gt215.c	18 Feb 2019 23:19:36 -0000	1.4
@@ -135,8 +135,9 @@ read_pll(struct gt215_clk *clk, int idx,
 		sclk = read_clk(clk, 0x10 + idx, false);
 	}
 
-	if (M * P)
-		return sclk * N / (M * P);
+	u32 mp = M * P;
+	if (mp != 0)
+		return sclk * N / mp;
 
 	return 0;
 }
Index: drm/nouveau/nvkm/subdev/mmu/nouveau_nvkm_subdev_mmu_base.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/mmu/nouveau_nvkm_subdev_mmu_base.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -p -u -r1.4 -r1.5
--- drm/nouveau/nvkm/subdev/mmu/nouveau_nvkm_subdev_mmu_base.c	1 Sep 2018 04:38:22 -0000	1.4
+++ drm/nouveau/nvkm/subdev/mmu/nouveau_nvkm_subdev_mmu_base.c	18 Mar 2019 02:01:41 -0000	1.5
@@ -528,6 +528,11 @@ nvkm_vm_del(struct kref *kref)
 
 	nvkm_mm_fini(&vm->mm);
 	vfree(vm->pgt);
+#ifdef __NetBSD__
+	linux_mutex_destroy(&vm->mutex);
+#else
+	mutex_destroy(&vm->mutex);
+#endif
 	kfree(vm);
 }
 
Index: drm/nouveau/nvkm/subdev/pci/nouveau_nvkm_subdev_pci_base.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pci/nouveau_nvkm_subdev_pci_base.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -p -u -r1.3 -r1.4
--- drm/nouveau/nvkm/subdev/pci/nouveau_nvkm_subdev_pci_base.c	27 Aug 2018 07:40:40 -0000	1.3
+++ drm/nouveau/nvkm/subdev/pci/nouveau_nvkm_subdev_pci_base.c	19 Dec 2018 09:20:56 -0000	1.4
@@ -142,9 +142,14 @@ nvkm_pci_init(struct nvkm_subdev *subdev
 #ifdef __NetBSD__
     {
 	const struct pci_attach_args *pa = &pdev->pd_pa;
+	int counts[PCI_INTR_TYPE_SIZE] =  {
+			[PCI_INTR_TYPE_INTX] = 1,
+			[PCI_INTR_TYPE_MSI] = 0,
+			[PCI_INTR_TYPE_MSIX] = 0,
+	};
 
 	/* XXX errno NetBSD->Linux */
-	ret = -pci_intr_alloc(pa, &pci->pci_ihp, NULL, 0);
+	ret = -pci_intr_alloc(pa, &pci->pci_ihp, counts, PCI_INTR_TYPE_INTX);
 	if (ret)
 		return ret;
 	pci->pci_intrcookie = pci_intr_establish_xname(pa->pa_pc,
Index: drm/radeon/radeon_display.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/radeon/radeon_display.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -p -u -r1.9 -r1.10
--- drm/radeon/radeon_display.c	27 Aug 2018 15:22:54 -0000	1.9
+++ drm/radeon/radeon_display.c	30 Jan 2019 01:11:08 -0000	1.10
@@ -188,36 +188,12 @@ static void legacy_crtc_load_lut(struct 
 		dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 
-	/*
-	 * At least the RV100 [vendor 1002 product 515e (rev. 0x02)]
-	 * has an old style palette
-	 */
-	if (rdev->family < CHIP_RV280) {
-#ifdef notyet
-		/*
-		 * Leave CLUT alone for now. The code below gives us a
-		 * nice 444 grayscale, but we are not in true color mode
-		 * anymore and I don't have any docs how to do this right.
-		 */
-		WREG8(RADEON_PALETTE_INDEX, 0);
-		for (i = 0; i < 256; i++) {
-#define R(x) (radeon_crtc->lut_r[i] >> 2)
-#define G(x) (radeon_crtc->lut_g[i] >> 2)
-#define B(x) (radeon_crtc->lut_b[i] >> 2)
-			WREG32(RADEON_PALETTE_DATA, ((R(i) << 16)
-				| (G(i) << 8) | B(i)) << 4);
-		}
-#else
-		printf("%s: unknown DAC, can't set lookup table\n", __func__);
-#endif
-	} else {
-		WREG8(RADEON_PALETTE_INDEX, 0);
-		for (i = 0; i < 256; i++) {
-			WREG32(RADEON_PALETTE_30_DATA,
-				     (radeon_crtc->lut_r[i] << 20) |
-				     (radeon_crtc->lut_g[i] << 10) |
-				     (radeon_crtc->lut_b[i] << 0));
-		}
+	WREG8(RADEON_PALETTE_INDEX, 0);
+	for (i = 0; i < 256; i++) {
+		WREG32(RADEON_PALETTE_30_DATA,
+			     (radeon_crtc->lut_r[i] << 20) |
+			     (radeon_crtc->lut_g[i] << 10) |
+			     (radeon_crtc->lut_b[i] << 0));
 	}
 }
 
Index: drm/radeon/radeon_evergreen_cs.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/radeon/radeon_evergreen_cs.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -p -u -r1.1 -r1.2
--- drm/radeon/radeon_evergreen_cs.c	27 Aug 2018 14:38:20 -0000	1.1
+++ drm/radeon/radeon_evergreen_cs.c	8 Feb 2019 04:11:53 -0000	1.2
@@ -1335,6 +1335,7 @@ static int evergreen_cs_handle_reg(struc
 			return -EINVAL;
 		}
 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
+		break;
 	case CB_TARGET_MASK:
 		track->cb_target_mask = radeon_get_ib_value(p, idx);
 		track->cb_dirty = true;
Index: drm/radeon/radeon_r300.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/radeon/radeon_r300.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -p -u -r1.1 -r1.2
--- drm/radeon/radeon_r300.c	27 Aug 2018 14:38:20 -0000	1.1
+++ drm/radeon/radeon_r300.c	8 Feb 2019 04:11:53 -0000	1.2
@@ -846,7 +846,7 @@ static int r300_packet0_check(struct rad
 					  ((idx_value >> 21) & 0xF));
 				return -EINVAL;
 			}
-			/* Pass through. */
+			/* FALLTHROUGH */
 		case 6:
 			track->cb[i].cpp = 4;
 			break;
@@ -997,7 +997,7 @@ static int r300_packet0_check(struct rad
 				return -EINVAL;
 			}
 			/* The same rules apply as for DXT3/5. */
-			/* Pass through. */
+			/* FALLTHROUGH */
 		case R300_TX_FORMAT_DXT3:
 		case R300_TX_FORMAT_DXT5:
 			track->textures[i].cpp = 1;
Index: drm/radeon/radeon_r420.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/radeon/radeon_r420.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -p -u -r1.1 -r1.2
--- drm/radeon/radeon_r420.c	27 Aug 2018 14:38:20 -0000	1.1
+++ drm/radeon/radeon_r420.c	8 Feb 2019 04:11:53 -0000	1.2
@@ -115,6 +115,7 @@ void r420_pipes_init(struct radeon_devic
 	default:
 		/* force to 1 pipe */
 		num_pipes = 1;
+		/* FALLTHROUGH */
 	case 1:
 		tmp = (0 << 1);
 		break;
Index: drm/ttm/ttm_bo.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/ttm/ttm_bo.c,v
retrieving revision 1.14
retrieving revision 1.15
diff -p -u -r1.14 -r1.15
--- drm/ttm/ttm_bo.c	27 Aug 2018 15:32:39 -0000	1.14
+++ drm/ttm/ttm_bo.c	2 Feb 2019 21:46:27 -0000	1.15
@@ -1624,10 +1624,6 @@ bool ttm_mem_reg_is_pci(struct ttm_bo_de
 
 void ttm_bo_unmap_virtual_locked(struct ttm_buffer_object *bo)
 {
-#ifndef __NetBSD__
-	struct ttm_bo_device *bdev = bo->bdev;
-#endif
-
 #ifdef __NetBSD__
 	if (bo->mem.bus.is_iomem) {
 		paddr_t start, end, pa;
@@ -1654,6 +1650,8 @@ void ttm_bo_unmap_virtual_locked(struct 
 		mutex_exit(bo->uvmobj.vmobjlock);
 	}
 #else
+	struct ttm_bo_device *bdev = bo->bdev;
+
 	drm_vma_node_unmap(&bo->vma_node, bdev->dev_mapping);
 #endif
 	ttm_mem_io_free_vm(bo);
Index: include/drm/drmP.h
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/include/drm/drmP.h,v
retrieving revision 1.34
retrieving revision 1.35
diff -p -u -r1.34 -r1.35
--- include/drm/drmP.h	28 Aug 2018 03:41:39 -0000	1.34
+++ include/drm/drmP.h	21 Dec 2018 07:51:18 -0000	1.35
@@ -710,6 +710,10 @@ struct drm_driver {
 	int num_ioctls;
 	const struct file_operations *fops;
 
+#ifdef __NetBSD__
+	int (*ioctl_override)(struct file *, unsigned long, void *);
+#endif
+
 	/* List of devices hanging off this driver with stealth attach. */
 	struct list_head legacy_dev_list;
 };
Index: include/drm/i915_pciids.h
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/include/drm/i915_pciids.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -p -u -r1.2 -r1.3
--- include/drm/i915_pciids.h	27 Aug 2018 04:58:38 -0000	1.2
+++ include/drm/i915_pciids.h	13 Sep 2018 08:25:55 -0000	1.3
@@ -285,10 +285,18 @@
 	INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
 	INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */ \
 
+#define INTEL_SKL_GT4_IDS(info) \
+	INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
+	INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
+	INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
+	INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
+	INTEL_VGA_DEVICE(0x193A, info)  /* SRV GT4e */
+
 #define INTEL_SKL_IDS(info) \
 	INTEL_SKL_GT1_IDS(info), \
 	INTEL_SKL_GT2_IDS(info), \
-	INTEL_SKL_GT3_IDS(info)
+	INTEL_SKL_GT3_IDS(info), \
+	INTEL_SKL_GT4_IDS(info)
 
 #define INTEL_BXT_IDS(info) \
 	INTEL_VGA_DEVICE(0x0A84, info), \
@@ -297,4 +305,40 @@
 	INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
 	INTEL_VGA_DEVICE(0x5A85, info)  /* APL HD Graphics 500 */
 
+#define INTEL_KBL_GT1_IDS(info)		\
+	INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
+	INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
+	INTEL_VGA_DEVICE(0x5917, info), /* DT  GT1.5 */ \
+	INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
+	INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
+	INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
+	INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
+	INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
+
+#define INTEL_KBL_GT2_IDS(info)		\
+	INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+	INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
+	INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
+	INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
+	INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
+	INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
+	INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
+
+#define INTEL_KBL_GT3_IDS(info)		\
+	INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
+	INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \
+	INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */
+
+#define INTEL_KBL_GT4_IDS(info)		\
+	INTEL_VGA_DEVICE(0x5932, info), /* DT  GT4 */ \
+	INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \
+	INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \
+	INTEL_VGA_DEVICE(0x593D, info)  /* WKS GT4 */
+
+#define INTEL_KBL_IDS(info) \
+	INTEL_KBL_GT1_IDS(info), \
+	INTEL_KBL_GT2_IDS(info), \
+	INTEL_KBL_GT3_IDS(info), \
+	INTEL_KBL_GT4_IDS(info)
+
 #endif /* _I915_PCIIDS_H */