Index: common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S
===================================================================
RCS file: /cvsroot/src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S,v
retrieving revision 1.5
diff -p -u -r1.5 __aarch64_lse.S
--- common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S	18 Jun 2022 08:01:56 -0000	1.5
+++ common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S	22 Jul 2022 22:58:23 -0000
@@ -64,21 +64,35 @@
 #if defined(AR_relax)
 #define ACQ
 #define REL
+#define BAR
 #endif
 
 #if defined(AR_acq)
 #define ACQ	a
 #define REL
+#define BAR
 #endif
 
 #if defined(AR_rel)
 #define ACQ
 #define REL	l
+#define BAR
 #endif
 
 #if defined(AR_acq_rel)
 #define ACQ	a
 #define REL	l
+#define BAR
+#endif
+
+#if defined(AR_sync)
+#define ACQ	a
+#ifdef L_swp
+#define REL
+#else
+#define REL	l
+#endif
+#define BAR	dmb ish
 #endif
 
 #if defined(OP_clr)
@@ -109,7 +123,11 @@
 #define SWP_FUNC		FUNC3
 #define INSN_FUNC		FUNC3
 
+#if defined(AR_sync)
+#define LDXR			_CONCAT3(ld, xr, OPSFX)
+#else
 #define LDXR			_CONCAT4(ld, ACQ, xr, OPSFX)
+#endif
 #define STXR			_CONCAT4(st, REL, xr, OPSFX)
 #define LDXP			_CONCAT3(ld, ACQ, xp)
 #define STXP			_CONCAT3(st, REL, xp)
@@ -135,6 +153,7 @@ ENTRY_NP(SWP_FUNC)
 #ifdef _HAVE_LSE
 	DO_LSE_INSN_IF_SUPPORTED(99f)
 	SWP	R0, R0, [x1]
+	BAR
 	ret
 99:
 #endif
@@ -142,6 +161,7 @@ ENTRY_NP(SWP_FUNC)
 1:	LDXR	R0, [x1]		/* load old value		 */
 	STXR	w3, R4, [x1]		/* store new value		 */
 	cbnz	w3, 2f			/*   succeed?? no, try again	 */
+	BAR				/* potential barrier		*/
 	ret				/* return old value		 */
 2:	b	1b
 END(SWP_FUNC)
@@ -161,7 +181,8 @@ ENTRY_NP(CAS_FUNC)
 	b.ne	2f			/*   not equal? return		*/
 	STXR	w3, R1, [x2]		/* store new value		*/
 	cbnz	w3, 3f			/*   succeed? nope, try again.	*/
-2:	ret				/* return.			*/
+2:	BAR				/* potential barrier		*/
+	ret				/* return.			*/
 3:	b	1b
 END(CAS_FUNC)
 #endif
@@ -183,7 +204,8 @@ ENTRY_NP(CASP_FUNC)
 	b.ne	2f			/*   not equal? return		*/
 	STXP	w7, x2, x3, [x4]	/* store new value		*/
 	cbnz	w7, 3f			/*   succeed? nope, try again.	*/
-2:	ret				/* return.			*/
+2:	BAR				/* potential barrier		*/
+	ret				/* return.			*/
 3:	b	1b
 END(CASP_FUNC)
 #endif
Index: common/lib/libc/arch/aarch64/atomic/Makefile.inc
===================================================================
RCS file: /cvsroot/src/common/lib/libc/arch/aarch64/atomic/Makefile.inc,v
retrieving revision 1.4
diff -p -u -r1.4 Makefile.inc
--- common/lib/libc/arch/aarch64/atomic/Makefile.inc	27 Apr 2021 09:14:24 -0000	1.4
+++ common/lib/libc/arch/aarch64/atomic/Makefile.inc	22 Jul 2022 22:58:23 -0000
@@ -14,7 +14,7 @@ SRCS.atomic+=	membar_ops.S
 #and cas nand or sub swap xor
 .for op in swp cas clr set eor add
 .for sz in 1 2 4 8
-.for ar in _relax _acq _rel _acq_rel
+.for ar in _relax _acq _rel _acq_rel _sync
 __aarch64_${op}${sz}${ar}.S: __aarch64_lse.S
 	${_MKTARGET_CREATE}
 	printf '#define OP ${op}\n#define OP_${op}\n#define SZ ${sz}\n#define AR ${ar}\n#define AR${ar}\n#include "__aarch64_lse.S"\n' > ${.TARGET}
@@ -23,7 +23,7 @@ SRCS.gen+=	__aarch64_${op}${sz}${ar}.S
 .endfor
 .endfor
 .for op in casp
-.for ar in _relax _acq _rel _acq_rel
+.for ar in _relax _acq _rel _acq_rel _sync
 __aarch64_${op}${ar}.S: __aarch64_lse.S
 	${_MKTARGET_CREATE}
 	printf '#define OP ${op}\n#define OP_${op}\n#define AR ${ar}\n#define AR${ar}\n#include "__aarch64_lse.S"\n' > ${.TARGET}