PCI configuration registers:
  Common header:
    0x00: 0x731f1002 0x00100007 0x030000c1 0x00800010

    Vendor Name: ATI Technologies (0x1002)
    Device Name: Radeon RX 5600 OEM/5600 XT / 5700/5700 XT (0x731f)
    Command register: 0x0007
      I/O space accesses: on
      Memory space accesses: on
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): off
      Fast back-to-back transactions: off
      Interrupt disable: off
    Status register: 0x0010
      Immediate Readiness: off
      Interrupt status: inactive
      Capability List support: on
      66 MHz capable: off
      User Definable Features (UDF) support: off
      Fast back-to-back capable: off
      Data parity error detected: off
      DEVSEL timing: fast (0x0)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: display (0x03)
    Subclass Name: VGA (0x00)
    Interface: 0x00
    Revision ID: 0xc1
    BIST: 0x00
    Header Type: 0x00+multifunction (0x80)
    Latency Timer: 0x00
    Cache Line Size: 64bytes (0x10)

  Type 0 ("normal" device) header:
    0x10: 0xc000000c 0x00000000 0xd000000c 0x00000000
    0x20: 0x0000e001 0xfbe00000 0x00000000 0xe4111da2
    0x30: 0xfbe80001 0x00000048 0x00000000 0x00000105

    Base address register at 0x10
      type: 64-bit prefetchable memory
      base: 0x00000000c0000000
    Base address register at 0x18
      type: 64-bit prefetchable memory
      base: 0x00000000d0000000
    Base address register at 0x20
      type: I/O
      base: 0x0000e000
    Base address register at 0x24
      type: 32-bit nonprefetchable memory
      base: 0xfbe00000
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x1da2
    Subsystem ID: 0xe411
    Expansion ROM Base Address Register: 0xfbe80001
      base: 0xfbe80000
      Expansion ROM Enable: on
      Validation Status: Validation not supported
      Validation Details: 0x0
    Capability list pointer: 0x48
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x00
    Minimum Grant: 0x00
    Interrupt pin: 0x01 (pin A)
    Interrupt line: 0x05

  Capability register at 0x48
    type: 0x09 (Vendor-specific)
  Capability register at 0x50
    type: 0x01 (Power Management)
  Capability register at 0x64
    type: 0x10 (PCI Express)
  Capability register at 0xa0
    type: 0x05 (MSI)

  PCI Power Management Capabilities Register
    Capabilities register: 0xf003
      Version: 1.2
      PME# clock: off
      Device specific initialization: off
      3.3V auxiliary current: self-powered
      D1 power management state support: off
      D2 power management state support: off
      PME# support D0: off
      PME# support D1: on
      PME# support D2: on
      PME# support D3 hot: on
      PME# support D3 cold: on
    Control/status register: 0x00000008
      Power state: D0
      PCI Express reserved: off
      No soft reset: on
      PME# assertion: disabled
      Data Select: 0
      Data Scale: 0
      PME# status: off
    Bridge Support Extensions register: 0x00
      B2/B3 support: off
      Bus Power/Clock Control Enable: off
    Data register: 0x00

  PCI Message Signaled Interrupt
    Message Control register: 0x0081
      MSI Enabled: on
      Multiple Message Capable: no (1 vector)
      Multiple Message Enabled: off (1 vector)
      64 Bit Address Capable: on
      Per-Vector Masking Capable: off
      Extended Message Data Capable: off
      Extended Message Data Enable: off
    Message Address (lower) register: 0xfee00000
    Message Address (upper) register: 0x00000000
    Message Data register: 0x0069

  PCI Vendor Specific Capabilities Register
    Capabilities length: 0x08

  PCI Express Capabilities Register
    Capability register: 0x0012
      Capability version: 2
      Device type: Legacy PCI Express Endpoint device
      Slot implemented: off
      Interrupt Message Number: 0x00
    Device Capabilities Register: 0x00008fa1
      Max Payload Size Supported: 256 bytes max
      Phantom Functions Supported: not available
      Extended Tag Field Supported: 8bit
      Endpoint L0 Acceptable Latency: 2us - 4us
      Endpoint L1 Acceptable Latency: More than 64us
      Attention Button Present: off
      Attention Indicator Present: off
      Power Indicator Present: off
      Role-Based Error Report: on
      Captured Slot Power Limit: 0W
      Function-Level Reset Capability: off
    Device Control Register: 0x2930
      Correctable Error Reporting Enable: off
      Non Fatal Error Reporting Enable: off
      Fatal Error Reporting Enable: off
      Unsupported Request Reporting Enable: off
      Enable Relaxed Ordering: on
      Max Payload Size: 256 byte
      Extended Tag Field Enable: on
      Phantom Functions Enable: off
      Aux Power PM Enable: off
      Enable No Snoop: on
      Max Read Request Size: 512 byte
    Device Status Register: 0x0009
      Correctable Error Detected: on
      Non Fatal Error Detected: off
      Fatal Error Detected: off
      Unsupported Request Detected: on
      Aux Power Detected: off
      Transaction Pending: off
      Emergency Power Reduction Detected: off
    Link Capabilities Register: 0x00400d04
      Maximum Link Speed: 16.0GT/s
      Maximum Link Width: x16 lanes
      Active State PM Support: L0s and L1 supported
      L0 Exit Latency: Less than 64ns
      L1 Exit Latency: Less than 1us
      Port Number: 0
      Clock Power Management: off
      Surprise Down Error Report: off
      Data Link Layer Link Active: off
      Link BW Notification Capable: off
      ASPM Optionally Compliance: on
    Link Control Register: 0x0040
      Active State PM Control: disabled
      Read Completion Boundary Control: 64bytes
      Link Disable: off
      Retrain Link: off
      Common Clock Configuration: on
      Extended Synch: off
      Enable Clock Power Management: off
      Hardware Autonomous Width Disable: off
      Link Bandwidth Management Interrupt Enable: off
      Link Autonomous Bandwidth Interrupt Enable: off
      DRS Signaling Control: not reported
    Link Status Register: 0x1104
      Negotiated Link Speed: 16.0GT/s
      Negotiated Link Width: x16 lanes
      Training Error: off
      Link Training: off
      Slot Clock Configuration: on
      Data Link Layer Link Active: off
      Link Bandwidth Management Status: off
      Link Autonomous Bandwidth Status: off
    Device Capabilities 2: 0x0073099f
      Completion Timeout Ranges Supported: ABCD
      Completion Timeout Disable Supported: on
      ARI Forwarding Supported: off
      AtomicOp Routing Supported: off
      32bit AtomicOp Completer Supported: on
      64bit AtomicOp Completer Supported: on
      128-bit CAS Completer Supported: off
      No RO-enabled PR-PR passing: off
      LTR Mechanism Supported: on
      TPH Completer Supported: Not supported
      LN System CLS: Not supported or not in effect
      10-bit Tag Completer Supported: on
      10-bit Tag Requester Supported: on
      OBFF Supported: Not supported
      Extended Fmt Field Supported: on
      End-End TLP Prefix Supported: on
      Max End-End TLP Prefixes: 1
      Emergency Power Reduction Supported: Not supported
      Emergency Power Reduction Initialization Required: off
      FRS Supported: off
    Device Control 2: 0x0400
      Completion Timeout Value: 50us to 50ms
      Completion Timeout Disabled: off
      ARI Forwarding Enabled: off
      AtomicOp Requester Enabled: off
      AtomicOp Egress Blocking: off
      IDO Request Enabled: off
      IDO Completion Enabled: off
      LTR Mechanism Enabled: on
      Emergency Power Reduction Request: off
      10-bit Tag Requester Enabled: off
      OBFF: Disabled
      End-End TLP Prefix Blocking on: off
    Link Capabilities 2: 0x0180001e
      Supported Link Speeds Vector: 2.5GT/s 5.0GT/s 8.0GT/s 16.0GT/s
      Crosslink Supported: off
      Lower SKP OS Generation Supported Speed Vector:
      Lower SKP OS Reception Supported Speed Vector:
      Retimer Presence Detect Supported: on
      DRS Supported: off
    Link Control 2: 0x0004
      Target Link Speed: 16.0GT/s
      Enter Compliance Enabled: off
      HW Autonomous Speed Disabled: off
      Selectable De-emphasis: -6dB
      Transmit Margin: 0
      Enter Modified Compliance: off
      Compliance SOS: off
      Compliance Preset/De-emphasis: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
    Link Status 2: 0x001f
      Current De-emphasis Level: -3.5dB
      Equalization Complete: on
      Equalization Phase 1 Successful: on
      Equalization Phase 2 Successful: on
      Equalization Phase 3 Successful: on
      Link Equalization Request: off
      Retimer Presence Detected: off

  Device-dependent header:
    0x40: 0x00000000 0x00000000 0x00085009 0xe4111da2
    0x50: 0xf0036401 0x00000008 0x00000000 0x00000000
    0x60: 0x00000000 0x0012a010 0x00008fa1 0x00092930
    0x70: 0x00400d04 0x11040040 0x00000000 0x00000000
    0x80: 0x00000000 0x00000000 0x0073099f 0x00000400
    0x90: 0x0180001e 0x001f0004 0x00000000 0x00000000
    0xa0: 0x00810005 0xfee00000 0x00000000 0x00000069
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x00000000 0x00000000 0x00000000 0x00000000

  Extended Capability Register at 0x100
    type: 0x000b (Vendor Unique)
    version: 1
  Extended Capability Register at 0x150
    type: 0x0001 (Advanced Error Reporting)
    version: 2
  Extended Capability Register at 0x200
    type: 0x0015 (Resizable BAR)
    version: 1
  Extended Capability Register at 0x240
    type: 0x0004 (Power Budgeting)
    version: 1
  Extended Capability Register at 0x270
    type: 0x0019 (Secondary PCI Express)
    version: 1
  Extended Capability Register at 0x2a0
    type: 0x000d (Access Control Services)
    version: 1
  Extended Capability Register at 0x2b0
    type: 0x000f (Address Translation Services)
    version: 1
  Extended Capability Register at 0x2c0
    type: 0x0013 (Page Request)
    version: 1
  Extended Capability Register at 0x2d0
    type: 0x001b (Process Address Space ID)
    version: 1
  Extended Capability Register at 0x320
    type: 0x0018 (Latency Tolerance Reporting)
    version: 1
  Extended Capability Register at 0x400
    type: 0x0025 (Data link Feature)
    version: 1
  Extended Capability Register at 0x410
    type: 0x0026 (Physical Layer 16.0 GT/s)
    version: 1
  Extended Capability Register at 0x440
    type: 0x0027 (Lane Margining at the Receiver)
    version: 1

  Advanced Error Reporting Register
    Uncorrectable Error Status register: 0x00000000
      Undefined: off
      Data Link Protocol Error: off
      Surprise Down Error: off
      Poisoned TLP Received: off
      Flow Control Protocol Error: off
      Completion Timeout: off
      Completer Abort: off
      Unexpected Completion: off
      Receiver Overflow: off
      Malformed TLP: off
      ECRC Error: off
      Unsupported Request Error: off
      ACS Violation: off
      Uncorrectable Internal Error: off
      MC Blocked TLP: off
      AtomicOp Egress BLK: off
      TLP Prefix Blocked Error: off
      Poisoned TLP Egress Blocked: off
    Uncorrectable Error Mask register: 0x00000000
      Undefined: off
      Data Link Protocol Error: off
      Surprise Down Error: off
      Poisoned TLP Received: off
      Flow Control Protocol Error: off
      Completion Timeout: off
      Completer Abort: off
      Unexpected Completion: off
      Receiver Overflow: off
      Malformed TLP: off
      ECRC Error: off
      Unsupported Request Error: off
      ACS Violation: off
      Uncorrectable Internal Error: off
      MC Blocked TLP: off
      AtomicOp Egress BLK: off
      TLP Prefix Blocked Error: off
      Poisoned TLP Egress Blocked: off
    Uncorrectable Error Severity register: 0x00462030
      Undefined: off
      Data Link Protocol Error: on
      Surprise Down Error: on
      Poisoned TLP Received: off
      Flow Control Protocol Error: on
      Completion Timeout: off
      Completer Abort: off
      Unexpected Completion: off
      Receiver Overflow: on
      Malformed TLP: on
      ECRC Error: off
      Unsupported Request Error: off
      ACS Violation: off
      Uncorrectable Internal Error: on
      MC Blocked TLP: off
      AtomicOp Egress BLK: off
      TLP Prefix Blocked Error: off
      Poisoned TLP Egress Blocked: off
    Correctable Error Status register: 0x00002000
      Receiver Error: off
      Bad TLP: off
      Bad DLLP: off
      REPLAY_NUM Rollover: off
      Replay Timer Timeout: off
      Advisory Non-Fatal Error: on
      Corrected Internal Error: off
      Header Log Overflow: off
    Correctable Error Mask register: 0x00002000
      Receiver Error: off
      Bad TLP: off
      Bad DLLP: off
      REPLAY_NUM Rollover: off
      Replay Timer Timeout: off
      Advisory Non-Fatal Error: on
      Corrected Internal Error: off
      Header Log Overflow: off
    Advanced Error Capabilities and Control register: 0x000000a0
      First Error Pointer: 0x0000
      ECRC Generation Capable: on
      ECRC Generation Enable: off
      ECRC Check Capable: on
      ECRC Check Enable: off
      Multiple Header Recording Capable: off
      Multiple Header Recording Enable: off
      Completion Timeout Prefix/Header Log Capable: off
      TLP Prefix Log Present: off
    Header Log register:
    0x16c: 0x00000000
    0x170: 0x00000000 0x00000000 0x00000000

  Power Budgeting
    Data Select register: 0x00000000
    Data register: 0x00078100
      Base Power: 0.0W
      PM Sub State: 0x0
      PM State: D0
      Type: Maximum
      Power Rail: Power(3.3V)
    Power Budget Capability register: 0x00000000
      System Allocated: off

  Access Control Services
    ACS Capability register: 0x00000000
      ACS Source Validation: off
      ACS Transaction Blocking: off
      ACS P2P Request Redirect: off
      ACS P2P Completion Redirect: off
      ACS Upstream Forwarding: off
      ACS Egress Control: off
      ACS Direct Translated P2P: off
      Egress Control Vector Size: 256
    ACS Control register: 0x00000000
      ACS Source Validation Enable: off
      ACS Transaction Blocking Enable: off
      ACS P2P Request Redirect Enable: off
      ACS P2P Completion Redirect Enable: off
      ACS Upstream Forwarding Enable: off
      ACS Egress Control Enable: off
      ACS Direct Translated P2P Enable: off

  Address Translation Services
    Capability register: 0x0020
      Invalidate Queue Depth: 32
      Page Aligned Request: on
      Global Invalidate: off
      Relaxed Ordering: off
    Control register: 0x0000
      Smallest Translation Unit: 0
      Enable: off

  Page Request
    Control Register: 0x0000
      Enable: off
      Reset: off
    Status Register: 0x0100
      Response Failure: off
      Unexpected Page Request Group Index: off
      Stopped: on
      PRG Response PASID Required: off
    Outstanding Page Request Capacity: 256
    Outstanding Page Request Allocation: 0

  Resizable BAR
    Number of Resizable BARs: 2
    Capability register(0): 0x0003f000
      Acceptable BAR sizes: 256MB 512MB 1GB 2GB 4GB 8GB
    Control register(0): 0x00000840
      BAR Index: 0
      BAR Size: 256MB
    Capability register(1): 0x00001fe0
      Acceptable BAR sizes: 2MB 4MB 8MB 16MB 32MB 64MB 128MB 256MB
    Control register(1): 0x00000102
      BAR Index: 2
      BAR Size: 2MB
    Capability register(2): 0x00000000
    Capability register(3): 0x00000000
    Capability register(4): 0x00000000
    Capability register(5): 0x00000000

  Latency Tolerance Reporting
    Max Snoop Latency Register: 0x1001
      Max Snoop Latency: 1048576ns
    Max No-Snoop Latency Register: 0x1001
      Max No-Snoop Latency: 1048576ns

  Secondary PCI Express Register
    Link Control 3 register: 0x00000000
      Perform Equalization: off
      Link Equalization Request Interrupt Enable: off
      Enable Lower SKP OS Generation Vector:
    Lane Error Status register: 0x00000000
    Equalization Control Register (Link 0): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 1): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 2): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 3): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 4): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 5): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 6): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 7): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 8): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 9): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 10): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 11): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 12): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 13): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 14): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7
    Equalization Control Register (Link 15): 0x7f00
      Downstream Port Transmit Preset: 0x0
      Downstream Port Receive Hint: 0x0
      Upstream Port Transmit Preset: 0xf
      Upstream Port Receive Hint: 0x7

  Process Address Space ID
    PASID Capability Register: 0x1006
      Execute Permission Supported: on
      Privileged Mode Supported: on
      Max PASID Width: 65535
    PASID Control Register: 0x0000
      PASID Enable: off
      Execute Permission Enable: off
      Privileged Mode Enable: off

  Data link Feature Register
    Capability register: 0x80000001
      Scaled Flow Control: on
      DLF Exchange enable: on
    Status register: 0x80000001
      Scaled Flow Control: on
      Remote DLF supported Valid: on

  Physical Layer 16.0 GT/s
    Capability register: 0x00000000
    Control register: 0x00000000
    Status register: 0x0000000f
      Equalization 16.0 GT/s Complete: on
      Equalization 16.0 GT/s Phase 1 Successful: on
      Equalization 16.0 GT/s Phase 2 Successful: on
      Equalization 16.0 GT/s Phase 3 Successful: on
    Local Data Parity Mismatch Status register: 0x00000000
    First Retimer Data Parity Mismatch Status register: 0x00000000
    Second Retimer Data Parity Mismatch Status register: 0x00000000
      Lane 0 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 0 upstream:   reserved value (0xf)
      Lane 1 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 1 upstream:   reserved value (0xf)
      Lane 2 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 2 upstream:   reserved value (0xf)
      Lane 3 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 3 upstream:   reserved value (0xf)
      Lane 4 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 4 upstream:   reserved value (0xf)
      Lane 5 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 5 upstream:   reserved value (0xf)
      Lane 6 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 6 upstream:   reserved value (0xf)
      Lane 7 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 7 upstream:   reserved value (0xf)
      Lane 8 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 8 upstream:   reserved value (0xf)
      Lane 9 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 9 upstream:   reserved value (0xf)
      Lane 10 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 10 upstream:   reserved value (0xf)
      Lane 11 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 11 upstream:   reserved value (0xf)
      Lane 12 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 12 upstream:   reserved value (0xf)
      Lane 13 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 13 upstream:   reserved value (0xf)
      Lane 14 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 14 upstream:   reserved value (0xf)
      Lane 15 downstream: Preshoot 0.0dB, De-emphasis -6.0+-1.5dB
      Lane 15 upstream:   reserved value (0xf)

  Lane Margining at the Receiver
    Port Capability register: 0x0000
      Margining uses Driver Software: off
    Port Status register: 0x0000
      Margining Ready: off
      Margining Software Ready: off
    Lane 0 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 0 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 1 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 1 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 2 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 2 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 3 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 3 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 4 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 4 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 5 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 5 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 6 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 6 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 7 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 7 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 8 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 8 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 9 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 9 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 10 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 10 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 11 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 11 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 12 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 12 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 13 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 13 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 14 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 14 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00
    Lane 15 control: 0x9c38
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 7
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x9c
    Lane 15 status: 0x0000
      Receive Number: Broadcast (Upstream Port Receiver)
      Margin Type: 0
      Usage Model: Lane Margining at Receiver
      Margin Payload: 0x00

  Extended Configuration Space:
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